Datasheet

VDRV
ADJ
R2
R1
 
 

SLVS367A − MARCH 2001 − REVISED JUNE 2001
15
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TYPICAL CHARACTERISTICS
Figure 20
VDRV LINE REGULATION
V
CC
− Supply Voltage − V
8.055
8.056
8.06
8.061
8.062
8.057
8.058
8.059
10 13
11 12 1514
C
L(VDRV)
= 1 µF
T
J
= 25°C
− Output Voltage − V
V
O
Figure 21
VDRV LOAD REGULATION
I
I
− Input Current − mA
8.085
8.09
8.11
8.115
8.095
8.1
8.105
−10 50
10 30 9070 110 150130
C
L(VDRV)
= 1 µF
T
J
= 25°C
− Output Voltage − V
V
O
APPLICATION INFORMATION
Figure 22 shows the circuit schematic of a 100-kHz synchronous-buck converter implemented with a TL5001ACD
pulse-width-modulation (PWM) controller and a TPS2838 driver. The converter operates over an input range from
4.5 V to 12 V and has a 3.3-V output. The circuit can supply 3-A continuous load. The converter achieves an efficiency
of 94% for V
IN
= 5 V, I
L
=1 A, and 93% for V
IN
= 5 V, I
L
= 3 A.
R1
(kΩ)
R2
(kΩ)
VDRV
Voltage
(V)
30 67 4
30 91 5
30 165 8
30 261 12
30 322 14.5
To set the regulator voltage (TPS2838/39) use the following equation:
R2 +
ǒ
R1
1.235
VDRV
Ǔ
* R1