Datasheet

5
4
7 3
8
1
2
2
BOOT
UGATE
PHASE
LGATE
GND
1
8
5
4
6 VDD
EN/PG
7
PWM
3
2
BOOT
UGATE
PHASE
LGATE
GND
1
8
5
4
6 VDD
EN
/PG
7
PWM
3
VIN
PWM 4
GND
VOUT
PWM1
8
PWM3
Enable
PWM2
ToDriver
ToDriver
GNDS
ToController
CSCNCS 4
ToController
CS 1
V
DD
(4.5Vto8V)
V
IN
(3Vto32V − V
DD
)
TPS28225
TPS28225
TPS4009x
oranyotheranalog
ordigitalcontroller
V
OUT
TPS28225
TPS28226
SLUS710C –MAY 2006–REVISED APRIL 2010 www.ti.com
TYPICAL APPLICATIONS (continued)
Multi-Phase Synchronous Buck Converter
ORDERING INFORMATION
(1) (2) (3)
PART NUMBER
TAPE AND REEL
TEMPERATURE RANGE, T
A
= T
J
PACKAGE
QTY.
TPS28225 TPS28226
Plastic 8-pin SOIC (D) 250 TPS28225DT TPS28226DT
Plastic 8-pin SOIC (D) 2500 TPS28225DR TPS28226DR
Plastic 8-pin DFN
-40°C to 125°C
250 TPS28225DRBT TPS28226DRBT
(DRB)
Plastic 8-pin DFN
3000 TPS28225DRBR TPS28226DRBR
(DRB)
(1) SOIC-8 (D) and DFN-8 (DRB) packages are available taped and reeled. Add T suffix to device type (e.g. TPS28225DT) to order taped
devices and suffix R to device type to order reeled devices.
(2) The SOIC-8 (D) and DFN-8 (DRB) package uses in Pb-Free lead finish of Pd-Ni-Au which is compatible with MSL level 1 at 255°C to
260°C peak reflow temperature to be compatible with either lead free or Sn/Pb soldering operations.
(3) In the DFN package, the pad underneath the center of the device is a thermal substrate. The PCB “thermal land” design for this
exposed die pad should include thermal vias that drop down and connect to one or more buried copper plane(s). This combination of
vias for vertical heat escape and buried planes for heat spreading allows the DFN to achieve its full thermal potential. This pad should
be either grounded for best noise immunity, and it should not be connected to other nodes.
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Product Folder Link(s): TPS28225 TPS28226