Datasheet

TPS28225

TPS28226

www.ti.com

SLUS710C –MAY 2006–REVISED APRIL 2010

Turning Off of the MOSFET needs to be done as fast as possible to reduce switching losses. For this reason the

TPS28225/6 driver has very low output impedance specified as 0.4Ω typ for lower driver and 1Ω typ for upper

driver at dc current. Assuming 8-V drive voltage and no parasitic inductances, one can expect an initial sink

current amplitude of 20A and 8A respectively for the lower and upper drivers. With pure R-C discharge circuit for

the gate capacitor, the voltage and current waveforms are expected to be exponential. However, because of

parasitic inductances, the actual waveforms have some ringing and the peak current for the lower driver is about

4A and about 2.5A for the upper driver (Figure 25 and Figure 26). The overall parasitic inductance for the lower

drive path is estimated as 4nH and for the upper drive path as 6nH. The internal parasitic inductance of the

driver, which includes inductances of bonded wires and package leads, can be estimated for SOIC-8 package as

2nH for lower gate and 4nH for the upper gate. Use of DFN-8 package reduces the internal parasitic inductances

by approximately 50%.

Layout Recommendations

To improve the switching characteristicsand efficiency of a design, the following layout rules need to be followed.

• Locate the driver as close as possible to the MOSFETs.

• Locate the V

and bootstrap capacitors as close as possible to the driver.

• Pay special attention to the GND trace. Use the thermal pad of the DFN-8 package as the GND by

connecting it to the GND pin. The GND trace or pad from the driver goes directly to the source of the

MOSFET but should not include the high current path of the main current flowing through the drain and

source of the MOSFET.

• Use a similar rule for the PHASE node as for the GND.

• Use wide traces for UGATE and LGATE closely following the related PHASE and GND traces. Eighty to 100

mils width is preferable where possible.

• Use at least 2 or more vias if the MOSFET driving trace needs to be routed from one layer to another. For the

GND the number of vias are determined not only by the parasitic inductance but also by the requirements for

the thermal pad.

• Avoid PWM and enable traces going close to the PHASE node and pad where high dV/dT voltage can induce

significant noise into the relatively high impedance leads.

It should be taken into account that poor layout can cause 3% to 5% less efficiency versus a good layout design

and can even decrease the reliability of the whole system.

Figure 27. One of Four Phases Driven by TPS28225/6 Driver in 4-phase VRM Reference Design

Product Folder Link(s): TPS28225 TPS28226