Datasheet

4
5
GND
6
VDD
LGATE
Cvdd
L bondwire
Rsink
Rsource
L pin
L trace
L bondwire
L bondwire
Driver
Output
Stage
L pin
L pin
L trace
Isink
L trace
Cgs
Rg
L trace
Isource
TPS28225
TPS28226
www.ti.com SLUS710C –MAY 2006–REVISED APRIL 2010
APPLICATION INFORMATION
Switching The MOSFETs
Driving the MOSFETs efficiently at high switching frequencies requires special attention to layout and the
reduction of parasitic inductances. Efforts need to be done both at the driver’s die and package level and at the
PCB layout level to keep the parasitic inductances as low as possible. Figure 24 shows the main parasitic
inductances and current flow during turning ON and OFF of the MOSFET by charging its C
GS
gate capacitance.
Figure 24. MOSFET Drive Paths and Main Circuit Parasitics
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