Datasheet

TPS28225

TPS28226

SLUS710C –MAY 2006–REVISED APRIL 2010

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3-State Input

As soon as the EN/PG pin is set high and input PWM pulses are initiated (see Note below). The dead-time

control circuit ensures that there is no overlapping between UGATE and LGATE drive outputs to eliminate shoot

through current through the external power FETs. Additionally to operate under periodical pulse sequencing, the

TPS28225/6 has a self-adjustable PWM 3-state input circuit. The 3-state circuit sets both gate drive outputs low,

and thus turns the external power FETs OFF if the input signal is in a high impedance state for at least 250 ns

typical. At this condition, the PWM input voltage level is defined by the internal 27kΩ to 13kΩ resistor divider

shown in the block diagram. This resistor divider forces the input voltage to move into the 3-state window. Initially

the 3-state window is set between 1.0-V and 2.0-V thresholds. The lower threshold of the 3-state window is

always fixed at about 1.0 V. The higher threshold is adjusted to about 75% of the input signal amplitude. The

self-adjustable upper threshold allows shorter delay if the input signal enters the 3-state window while the input

signal was high, thus keeping the high-side power FET in ON state just slightly longer than 250 ns time constant

set by an internal 3-state timer. Both modes of operation, PWM input pulse sequencing and the 3-state condition,

are illustrated in the timing diagrams shown in Figure 18. The self-adjustable upper threshold allows operation in

wide range amplitude of input PWM pulse signals. The waveforms in Figure 20 and Figure 21 illustrates the

TPS28225 operation at normal and 3-state mode with the input pulse amplitudes 6 V and 2.5 V accordingly. After

entering into the 3-state window and staying within the window for the hold-off time, the PWM input signal level is

defined by the internal resistor divider and, depending on the input pulse amplitude, can be pulled up above the

normal PWM pulse amplitude (Figure 21) or down below the normal input PWM pulse (Figure 20).

TPS28225 3-State Exit Mode:

• To exit the 3-state operation mode, the PWM signal should go low and then high at least once.

TPS28226 3-State Exit Mode:

• To exit the 3-state operation mode, the PWM signal should go high and then low at least once.

This is necessary to restore the voltage across the bootstrap capacitor that could be discharged during the

3-state mode if the 3-state condition lasts long enough.

Figure 20. 6-V Amplitude PWM Pulse (TPS28225) Figure 21. 2.5-V Amplitude PWM Pulse (TPS28225)

NOTE

The driver sets UGATE low and LGATE high when PWM is low. When the PWM goes

high, UGATE goes high and LGATE goes low.

Product Folder Link(s): TPS28225 TPS28226