Datasheet

Thermal SD
UVLO
7
EN/PG
6
System
Controller
. 20 kΩ
V
CC
V
DD
= 4.5 V to 8 V for the TPS28225 or
6.8 V to 8.0 V for the TPS28226
Driver TPS28225
1 kΩ
1 M
R
DS(on)
= 1 kΩ
2 V Rise
1 V Fall
TPS28225
TPS28226
www.ti.com SLUS710C –MAY 2006–REVISED APRIL 2010
Enable/Power Good
The Enable/Power Good circuit allows the TPS28225/6 to follow the PWM input signal when the voltage at
EN/PG pin is above 2.1 V maximum. This circuit has a unique two-way communication capability. This is
illustrated by Figure 19.
Figure 19. Enable/Power Good Circuit
The EN/PG pin has approximately 1-kΩ internal series resistor. Pulling EN/PG high by an external ≥ 20-kΩ
resistor allows two-way communication between controller and driver. If the input voltage V
DD
is below UVLO
threshold or thermal shut down occurs, the internal MOSFET pulls EN/PG pin to GND through 1-kΩ resistor. The
voltage across the EN/PG pin is now defined by the resistor divider comprised by the external pull up resistor,
1-kΩ internal resistor and the internal FET having 1-kΩ R
DS(on)
. Even if the system controller allows the driver to
start by setting its own enable output transistor OFF, the driver keeps the voltage at EN/PG low. Low EN/PG
signal indicates that the driver is not ready yet because the supply voltage V
DD
is low or that the driver is in
thermal shutdown mode. The system controller can arrange the delay of PWM input signals coming to the driver
until the driver releases EN/PG pin. If the input voltage V
DD
is back to normal, or the driver is cooled down below
its lower thermal shutdown threshold, then the internal MOSFET releases the EN/PG pin and normal operation
resumes under the external Enable signal applied to EN/PG input. Another feature includes an internal 1-MΩ
resistor that pulls EN/PG pin low and disables the driver in case the system controller accidentally loses
connection with the driver. This could happen if, for example, the system controller is located on a separate PCB
daughter board.
The EN/PG pin can serve as the second pulse input of the driver additionally to PWM input. The delay between
EN/PG and the UGATE going high, provided that PWM input is also high, is only about 30ns. If the PWM input
pulses are synchronized with EN/PG input, then when PWM and EN/PG are high, the UGATE is high and
LGATE is low. If both PWM and EN/PG are low, then UGATE and LGATE are both low as well. This means the
driver allows operation of a synchronous buck regulator as a convertional buck regulator using the body diode of
the low side power MOSFET as the freewheeling diode. This feature can be useful in some specific applications
to allow startup with a pre-biased output or, to improve the efficiency of buck regulator when in power saving
mode with low output current.
Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback 17
Product Folder Link(s): TPS28225 TPS28226