Datasheet

TPS28225

TPS28226

SLUS710C –MAY 2006–REVISED APRIL 2010

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DETAILED DESCRIPTION

Under Voltage Lockout (UVLO)

The TPS28225/6 incorporates an under voltage lockout circuit that keeps the driver disabled and external power

FETs in an OFF state when the input supply voltage V

is insufficient to drive external power FETs reliably.

During power up, both gate drive outputs remain low until voltage V

reaches UVLO threshold, typically 3.5 V

for the TPS28225/6 and and 6.35 V for the TPS28226. Once the UVLO threshold is reached, the condition of

gate drive outputs is defined by the input PWM and EN/PG signals. During power down the UVLO threshold is

set lower, typically 3.0 V for the TPS28225/6 and 5.0 V for the TPS28226. The 0.5-V for the TPS28225/6 and

1.35 V for the TPS28226 hysteresis is selected to prevent the driver from turning ON and OFF while the input

voltage crosses UVLO thresholds, especially with low slew rate. The TPS28225/6 has the ability to send a signal

back to the system controller that the input supply voltage V

is insufficient by internally pulling down the EN/PG

pin. The TPS28225/6 releases EN/PG pin immediately after the V

has risen above the UVLO threshold.

Output Active Low

The output active low circuit effectively keeps the gate outputs low even if the driver is not powered up. This

prevents open gate conditions on the external power FETs and accidental turn ON when the main power stage

supply voltage is applied before the driver is powered up. For the simplicity, the output active low circuit is shown

in a block diagram as the resistor connected between LGATE and GND pins with another one connected

between UGATE and PHASE pins.

Product Folder Link(s): TPS28225 TPS28226