Datasheet

( )
J(MAX)
(MAX)
JA
T T
A
PD
-
=
q
TPS27082L
SLVSBR5B –DECEMBER 2012–REVISED SEPTEMBER 2013 www.ti.com
Table 1. Capacitor C1 Selection for Standard Output Rise Time
C1 (F)
t
rise
R1 = 125 kΩ
(µSec)
(Typical)
VIN=7V VIN=5V VIN=3.3V VIN=1.8V VIN=1.2V
5 0 0 0 0 0
50 3.46n 2.77n 2.10n 1.41n 1.08n
100 6.91n 5.54n 4.21n 2.82n 2.16n
250 17.3n 13.8n 10.5n 7.05n 5.40n
470 32.5n 26.0n 19.8n 13.3n 10.1n
1000 69.1n 55.4n 42.1n 28.2n 21.6n
Note: The t
rise
equation and the capacitor C1 values recommended in the table above are under typical
conditions and are accurate to within ±20%. Ensure R1 > 125kΩ; and select a closest standard valued capacitor
C1.
Configuring Turn-OFF delay
TPS27082L PMOS turn-OFF delay from the falling edge of ON/OFF logic signal depends upon the component
values of resistor R1 and capacitor C1. Lower values of resistor R1 ensures quicker turn-OFF.
t
off
> (R1 × C1 sec) (4)
OFF Isolation Under VIN Transients
TPS27082L architecture helps isolate fast transients at the VIN when PFET is in the OFF state. Best transient
isolation is achieved when an external capacitor C1 is not connected across VOUT and R1/C1 pins. When a
capacitor C1 is present the VIN to VOUT coupling is capacitive and is set by the C1 to CL capacitance ratio.
TPS27082L architecture prevents direct conduction through PFET.
Low Voltage ON/OFF Interface
To turn ON the load switch apply a voltage > 1.0V at the ON/OFF pin. The TPS27082L features hysteresis at its
ON/OFF input. The turn-ON and turn-OFF thresholds are dependent upon the value of resistor R1. Refer to the
ELECTRICAL CHARACTERISTICS Table and Figure 14 for details on the positive and negative going ON/OFF
thresholds.
In applications where ON/OFF signal is not available connect ON/OFF pin to the VIN pin. The TPS27082L will
turn ON and OFF in sync with the input supply connected to VIN.
On-chip Power Dissipation
Use below approximate equation to calculate TPS27082L’s on-chip power dissipation P
D
:
PD = ID
Q1
2
× R
Q1(ON)
(5)
Where, ID
Q1
is the DC current flowing through the transistor Q1. Refer to the ELECTRICAL CHARACTERISTICS
Table and the Figure 16 through Figure 22 to estimate R
Q1(ON)
for various values of VGSQ1.
Note: MOS switches can get extremely hot when operated in saturation region. As a general guideline, to avoid
transistors Q1 going into saturation region set VGS > VDS+1.0V. E.g. VGS > 1.5V and VDS < 200mV ensures
switching region.
Thermal Reliability
For higher reliability it is recommended to limit TPS27082L IC’s die junction temperature to less than 125°C. The
IC junction temperature is directly proportional to the on-chip power dissipation. Use the following equation to
calculate maximum on-chip power dissipation to restrict the die junction temperature target to safe limits:
(6)
Where T
J(MAX)
is the target maximum junction temperature, T
A
is the operating ambient temperature, and θ
JA
is
the package junction to ambient thermal resistance.
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