Datasheet

3
rise
2/3
50 10 C1
t   sec
VIN
´ ´
= 
final initial
inrush load load
VOUT –VOUT 
dv
I C C
dt Vout Slew  Rate
´ ´= =
Q1
R1
VGS VIN V
R1 12.5 k
= - ´
+ Ω
ESD
ESD
ESD
Logic &
Control
TPS27082L
(4)
(6)
(5)
(2, 3)
RS=12.5kΩ
C1
VOUT
VIN
R1/C1
ON/OFF
R1
GND
(1)
ESD
Q1
Q2
TPS27082L
www.ti.com SLVSBR5B –DECEMBER 2012–REVISED SEPTEMBER 2013
APPLICATION INFORMATION
The TPS27082L IC is a high side load switch that integrates a Power PFET and its control circuit in a tiny TSOT-
23 package. TPS27082L supports up to 8V supply input and up to 3A of load current. The TPS27082L can be
used in a variety of applications. Figure 1 shows a general application of TPS27082L to control capacitive load
inrush current.
Figure 1. Typical Application Diagram
Configuring Q1 ON resistance
V
GS-Q1
, Gate-Source voltage, of PMOS transistor Q1 sets its ON resistance R
Q1(ON)
. Connecting a high value pull
up resistor R1 maximizes ON state V
GS-Q1
and thus minimizes the VIN to VOUT voltage drop. Use the following
equation for calculating V
GS-Q1
:
(1)
e.g. R1= 125kΩ, VIN = 5V sets VGS
Q1
= -4.5V
NOTE
It is recommended to keep R1 ≥ 125 kΩ. Higher value resistor R1 reduces ON-state
quiescent current, increases turn-OFF delay, while reducing ON/OFF negative going
threshold voltage V
T–
.
Configuring Turn-ON slew rate
Switching a large capacitive load CL instantaneously results in a load inrush current given by the following
equation:
(2)
An uncontrolled fast rising ON/OFF logic input may result in a high slew rate (dv/dt)at the output thus leading to a
higher load inrush current. To control the inrush current connect a capacitor C1 as shown in the Figure 1. Use
the following approximate empirical equation to configure the TPS27082L slew rate to a specific value.
(3)
Where
trise
is the time delta starting from the ON/OFF signal’s rising edge to charge up the load capacitor CL
from 10% to 90% of VIN voltage.
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