Datasheet

ESD
ESD
ESD
Logic &
Control
TPS27082L
(4)
(6)
(5)
(2, 3)
RS=12.5kΩ
C1
VOUT
VIN
R1/C1
ON/OFF
R1
GND
(1)
ESD
Q1
Q2
VOUT
1
2
3
GND
VOUT
VIN
6
5
4
R1/C1
ON/OFF
TPS27082LDDC
(TOP VIEW)
2.9mm x 1.6mm x 0.75mm
TSOT-23(DDC)
TPS27082L
SLVSBR5B –DECEMBER 2012–REVISED SEPTEMBER 2013 www.ti.com
TPS27082LD and TPS27082LDRV PINOUT
PIN FUNCTIONS
PIN
NAME NO. DESCRIPTION
GND 1 Connect to the system GND
VOUT 2, 3 Drain Terminal of Power PFET (Q1) – If required, connect a slew control capacitor between pins VOUT and R1/C
VIN 4 Source Terminal of Power PFET (Q1) – connect a pull-up resistor between the pins VIN and R1/C1
ON/OFF 5 Active high enable – when driven with a high impedance driver, connect an external pull down resistor to GND
R1/C1 6 Gate Terminal of Power PFET (Q1)
Typical Application Diagram
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