Datasheet

TPS27081A
SLVSBE9D –APRIL 2012–REVISED APRIL 2013 www.ti.com
Table 1. Component Values for VOUT Rise Time
Rise Time (µs)
(2)(3)
R1=10kΩ, R2=1kΩ R1=5.1kΩ, R2=510Ω
C1
(1)
VIN = VIN =
VIN = 7V VIN = 5V VIN = 7V VIN = 5V VIN = 3.3V VIN = 1.2V
3.3V 1.2V
220pF .253 .316 .416 .810 .129 .161 .212 .413
1000pF 1.15 1.44 1.89 3.68 .586 .732 .963 1.88
4700pF 5.4 6.75 8.88 17.3 2.76 3.44 4.53 8.83
0.18uF 207 258 340 663 106 132 173 338
0.27uF 310 388 510 994 158 198 260 507
0.33uF 379 474 623 1220 194 242 318 620
1uF 1150 1440 1890 3680 586 732 963 1880
(1) Typical ceramic capacitor values
(2) CLoad=10uF. Output rise time is independent of CLoad when CLoad >> C1
(3) Rise Time is 250ns for R2=0Ω and C1=CLoad=0F
Configuring Turn-OFF Delay
TPS27081A PMOS turn-off delay from the falling edge of ON/OFF logic signal depends upon the component
values of resistor R1 & capacitor C1. Lower values of resistor R1 ensures quicker turn-off.
t
off
> 2 × R1 × C1 sec
Low Voltage ON/OFF Interface
The VGS
Q2
is set by the ON/OFF logic level. To turn ON, the transistor Q2 requires a VGS > 1.0V (Typical). For
reliable operation apply ON/OFF logic that has the following VIH and VIL limits:
VIH
ON
> 1.0V + I
Q2
× R2 V
VIL
OFF
< 0.2 V
Minimizing I
Q2
x R2 drop helps achieve a direct interface with a low voltage ON/OFF logic. To minimize I
Q2
x R2
voltage drop select a high R1/R2 ratio. E.g. When VIN= 1.8V, selecting R1/R2 = 40 will require V
IH
> 1.0 + 45mV
and thus allowing a 1.2V GPIO interface.
In applications where ON/OFF signal is not available connect ON/OFF pin to VIN. The TPS27081A will turn
ON/OFF in sync with the input supply connected to VIN.
Note: Connect a pull down resistor between ON/OFF pin to GND when ON/OFF is driven by a high-impedance
(tri-state) driver.
On-Chip Power Dissipation
Use the below equation to calculate TPS27081A on-chip power dissipation P
D
:
PD = ID
Q1
2
× R
Q1(ON)
+ID
Q2
2
× R
Q2(ON)
Where, ID
Q1
and ID
Q2
are the DC current flowing through the transistors Q1 and Q2 respectively. Refer to the
ELECTRICAL CHARACTERISTICS table and/or Figure 10 through Figure 16 to estimate R
Q1(ON)
and R
Q2(ON)
for
various values of VGS
Q1
and VGS
Q2
respectively.
Note: MOS switches can get extremely hot when operated in saturation region. As a general guideline, to avoid
transistors Q1 and Q2 going into saturation region set VGS > VT +VDS. E.g. VGS > 1.5V and VDS < 200mV
ensures operation as a switch.
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