Datasheet
TPS27081A
SLVSBE9D –APRIL 2012–REVISED APRIL 2013
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION
(1)
T
A
PART NUMBER PACKAGE TOP-SIDE MARKING
(2)
–40°C to 85°C TPS27081ADDCR 6-Pin Thin SOT Reel of 3000 AU_
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
(2) DDC: The actual top-side marking has one additional character that designates the wafer fab/assembly site.
ABSOLUTE MAXIMUM RATINGS
(1)(2)
Specified at T
J
= –40°C to 105°C unless otherwise noted.
VALUE
UNIT
MIN MAX
V
INmax
,
V
IN
, V
OUT
pin Maximum Voltage with reference to pin R2 –0.1 8 V
V
OUTmax
V
ON/OFF
ON/OFF Pin max Voltage with respect to Pin R2 –0.3 8 V
Max Continuous Drain Current of Q1 at T
J
= 105°C 3
I
Q1-ON
A
Max Pulsed Drain Current of Q1
(3)
at T
J
= 105°C 9.5
Max power dissipation at T
A
P
D
6 Pin - TSOT, θ
JA
= 105°C/W 1190 mW
= 25°C, T
J
= 150°C
ESD Rating – HBM 2000
All pins V
ESD Rating – CDM 500
T
A
Operating free-air ambient temperature range –40 85
(4)
°C
T
J-max
(5)
Operating virtual junction temperature 150 °C
T
stg
Storage temperature range –65 150 °C
(1) Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these conditions is not implied. Exposure to absolute-maximum-rated conditions for
extended periods may affect device reliability.
(2) Refer to TI’s design support web page at www.ti.com/thermal for improving device thermal performance
(3) Pulse Width <300us, Duty Cycle <2%
(4) TJ-max limits and other related conditions apply. Refer to SOA charts, Figure 17 through Figure 21
(5) Operating at the absolute T
J-max
of 150°C can affect reliability – for higher reliability it is recommended to ensure T
J
<105°C
DISSIPATION RATINGS
(1)(2)(3)
BOARD PACKAGE θ
JC
θ
JA
(4)
T
A
< 25°C T
A
= 70°C T
A
= 85°C DERATING FACTOR
ABOVE T
A
= 25ºC
High- 6-Pin Thin SOT 43°C/W 105°C/W 1190 mW 760 mW 619 mW 9.55 mW/°C
K(JEDEC 51- (DDC)
7)
(1) Refer to TI’s design support web page at www.ti.com/thermal for improving device thermal performance.
(2) Maximum dissipation values for retaining a maximum allowable device junction temperature of 150°C
(3) Package thermal data based on a 76x114x1.6mm, 4-layer board with 2-oz Copper on outer layers
(4) Operating at the absolute TJ-max of 150°C can affect reliability; TJ ≤ 105°C is recommended
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