Datasheet

TPS2540, TPS2540A

TPS2541, TPS2541A

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SLVSAG2C –OCTOBER 2010– REVISED OCTOBER 2011

Layout Guidelines

TPS2540/40A/41/41A Placement: Place the TPS2540/40A/41/41A near the USB output connector and 150-µF

OUT pin filter capacitor. Connect the exposed Power PAD to the GND pin and to the system ground plane using

a via array.

IN Pin Bypass Capacitance: Place the 0.1-µF bypass capacitor near the IN pin and make the connection using

a low inductance trace.

D+ and D- Traces: Route in and out traces as controlled impedance differential pairs per the USB specification

and the Intel guideline for USB-2.0. Minimize the use of vias in the high speed data lines.

ESD

The use of a common mode choke in the upstream datapath can provide additional ESD protection from client

side cable insertion transients. In addition, a low capacitance ESD protection array such as the TPD2E001

provides a robust solution. The TPS2540EVM-623 (SLVU401) provides a good example of routing and output

datapath protection.

Using a system board, applying same design rules and protection devices as the TPS2540EVM-623 , the

TPS2540 has been tested to EN61000-4-2. The levels used were 8-kV contact discharge and 15-kV air

discharge. Voltage transients were applied between D+ terminal and the earth ground, and between D- terminal

and the earth ground, V- being connected to earth ground. Tests were performed while both powered and

unpowered. No TPS2540 failures were observed and operation was continuous.

ILIM0 and ILIM1 Pin Connections

Current limit set point accuracy can be compromised by stray leakage from a higher voltage source to the ILIM0

or ILIM1 pins. Ensure that there is adequate spacing between IN pin copper/trace and ILIM0 pin trace to prevent

contaminant buildup during the PCB assembly process. If a low current limit set point is required (RILIMx > 200

kΩ), use ILIM1 for this case as it is further away from the IN pin.

Product Folder Link(s): TPS2540, TPS2540A TPS2541, TPS2541A