Datasheet

EVM Assembly Drawings and Layout Guidelines

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4 EVM Assembly Drawings and Layout Guidelines

4.1 Layout Guidelines

• TPS2540/40A/41/41A placement: Place the TPS2540/41 near the USB output connector and 150µF

OUT pin filter capacitor. Connect the exposed pad to the GND pin and the system ground plane using

an array of vias.

• IN pin bypass capacitance: Place the 0.1µF bypass capacitor near the IN pin and make the connection

using a low inductance trace.

• DP-OUT/DM-OUT, DP-IN/DM-IN traces: Route these traces as controlled impedance differential pairs

per the USB-2.0 specification. Minimize the use of vias in the high speed data lines. Figure 6 provides

a good signal routing example for the high speed data traces. In this example, the data pairs are

routed as edge-coupled microstrips with nominal differential impedance of 90 ohms. The reference

plane is tied to GND and is shown in Figure 5. Ensure that the reference plane is void of cuts or splits

above the differential pairs to prevent impedance discontinuities.

• ILIM0 and ILIM1 Pin Connections: Current-limit, set-point accuracy can be compromised by stray

current leakage from a higher voltage source to the ILIM0 or ILIM1 pins. Ensure that there is adequate

spacing between IN pin copper/trace and ILIM0 pin trace to prevent contaminant buildup during the

PCB assembly process. If a low-current-limit set point is required (RILIMx > 200 kΩ), use ILIM1 for this

case as it is further away from the IN pin.

4.2 PCB Drawings

The following figures show component placement and layout of the EVM.

Figure 3. Top Side Placement and Routing

TPS2540EVM-623: Evaluation Module for TPS2540/40A and TPS2541/41A SLVU401B–September 2010–Revised August 2011

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