Datasheet

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IMON VCC SENSE
VCC SENSE
V Gain V Offset
Linearity(%) 100
Gain V Offset
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TPS2492
TPS2493
www.ti.com SLUSA65C –JULY 2010–REVISED JANUARY 2013
PG: The power good output is an active low, open-drain output intended to interface to downstream DC-to-DC
converters or monitoring circuits. PG goes low after V
DS
of M1 has fallen to about 1.25 V and a 9-ms deglitch
time period has elapsed. PG is open drain whenever UVEN is low, V
DS
of M1 is above 2.7 V, or UVLO is active.
PG can also be viewed as having an output voltage monitor function. The 9-ms deglitch circuit operates to filter
short events that could cause PG to go inactive (open drain) such as a momentary overload or input voltage
step. V
PG
can be greater than V
VCC
because it’s ESD protection is only with respect to ground. PG may be left
open or tied to GND if not used.
GND: This pin is connected to system ground.
IMON: This current monitor output has a voltage equal to 48 times the voltage across R
SENSE
(V
VCC-SENSE
). IMON
is clamped at 2.7 V to prevent damage to downstream A/D circuits. IMON is a voltage output and does not
require a pull up or pull down. IMON will have a small amount of superimposed ripple at 2.5 kHz that is an
artifact of the monitoring circuit. The error due to the ripple does not significantly effect accuracy for signals on
the order of 1 V, but better accuracy may be achieved for small signals with an external R-C filter. The IMON pull
up source is stronger than the pull down. A resistor pull down can be used to improve transient response in
designs with large filter capacitors. Leave IMON open if not used.
A curve of Linearity (%) versus V
VCC-SENSE
is provided in the Typical Characteristics, providing an indication of
error versus signal level. This curve is constructed by first performing a first order curve fit to V
IMON
versus V
VCC-
SENSE
, yielding Gain and Offset terms for the linear fit. The Linearity (%) plot is calculated as:
(4)
FLT: This active low, open drain output asserts (goes low) when the fault timer expires after a prolonged over
current or an OV is detected. FLT is open drain whenever UVEN, POR, or UVLO are not satisfied. FLT is latched
in the TPS2492, clearing when the latch is reset. FLT clears automatically in the TPS2493 when a power-up retry
occurs. V
FLT
can be greater than V
VCC
because it's ESD protection is only with respect to ground. FLT may be
left open or tied to GND when not used.
OV: The over-voltage monitoring pin is programed with a resistor divider such as R1 - R3 in the Typical
Application Circuit. This function forces GATE and FLT low while the OV condition exists. While V
OV
exceeds its
threshold, the strong GATE pull down (125 mA) is applied for up to 100 µs, followed by the 2 mA pull down. The
GATE pull down and FLT are released as soon as the OV condition is cleared. Tie OV to GND if not used.
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