Datasheet

´
= -
GATE ON
G GD
VCC
I t
C C
V
´
=
O VCC
ON
CHARGE
C V
t
I
( )
R1= R1+R2 R2 9 7407 0 4133 9 3275- = W - W = W. k . k . k
( )
R2= R2+R3 R3 1 4133 1 0 4133- = W - W = W. k k . k
( )
( )
( )
( )
UVEN_H
UV
V 1 2 3
1 25 9 7407 1
R2+R3 1 4133
V 9 5
´ + +
´ W + W
= = = W
R R R
. V . k k
. k
. V
( )
( )
( )
OV OV_H
UV_H
R3 V -V
1 14 5 1 35
R1+R2 9 7407
1 35
V
´
W ´ -
= = = W
k . V . V
. k
. V
( )
( )
R2+R3
R1+R2+R3
´
=
UV
UVEN _ H
V
V
( )
R3
R1+R2+R3
´
=
OV
OV _ H
V
V
TPS2492
TPS2493
SLUSA65C –JULY 2010–REVISED JANUARY 2013 www.ti.com
5. Choose the Turn-On and Over-voltage Divider, R
1
- R
3
Per our system design requirements above, both over-voltage shutdown and under-voltage shutdown are
desired. Equations for calculating the thresholds are:
(17)
(18)
Assume R3 is 1 kΩ and use the following procedure to determine R1 and R2.
(19)
(20)
(21)
(22)
Selecting standard 1% values and scaling up by a factor of 10 to reduce power loss results in (R1 = 93.1 kΩ),
(R2 = 4.12 kΩ), and (R3 = 10 kΩ).
Alternative Inrush Designs
Gate Capacitor (dV/dt) Control
The TPS2492/93 can be used with applications that require constant turn-on currents. The current is controlled
by a single capacitor from the GATE terminal to ground with a series resistor. M1 appears to operate as a source
follower (following the gate voltage) in this implementation. Again assuming that the output capacitor charges
without additional loading, choose a time to charge, t
ON
, based on the load capacitor, C
O
input voltage V
I
, and
desired charge current I
CHARGE
. When power limiting is used (V
PROG
< V
REF
) choose I
CHARGE
to be less than P
LIM
/V
VCC
to prevent the fault timer from starting. The fault timer starts only if power or current limit is invoked.
(23)
Use the following equation to select the gate capacitance, C
G
. It has been assumed that the external added
(linear) capacitor is much larger than the FET capacitance. C
GD
is the gate capacitance of M1, and I
GATE
is the
TPS2492/93 nominal gate charge current. C
GD
is non-linear with applied V
DG
. An averaged estimate may be
made using the FET V
GS
vs Q
G
curve. Divide the charge accumulated during the plateau region by the plateau
V
GS
to get C
GD
. As shown in Figure 19, a series resistor of about 1 kΩ should be used in series with C
G
to avoid
slowing the turnoff.
(24)
If neither power nor current limit faults are invoked during turn on, C
T
can be chosen for fast transient turnoff
response. Considerations are junction temperature rise (as above), anticipated system noise, and possible peak
overloads due to input voltage or load transients. Generally the period should be much less than the t
ON
of step 4
above.
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