Datasheet

TPS2492
TPS2493
SLUSA65C –JULY 2010–REVISED JANUARY 2013 www.ti.com
Response to a Hard Output Short (Figure 15, Figure 16, and Figure 17)
Figure 15 shows the short circuit response over the full time-out period. An output short is applied, causing the
voltage to fall, limiter action begin, and the fault timer to start. The external FET current is actively controlled by
the power limiting engine and gate amplifier circuit while the TIMER pin charges C
T
to the 4-V threshold. Once
this threshold is reached, the TPS2492/93 turns off the external FET. The TPS2492 latches off until either the
input voltage drops below the UVLO threshold or UVEN cycles through the false (low) state. The TPS2493 will
attempt a restart after going through a timing cycle. Figure 16 demonstrates the operation of FLT during a short
circuit. FLT remains false (open drain) until the TIMER has expired.
Figure 15. Current Limit Overview
16 Submit Documentation Feedback Copyright © 2010–2013, Texas Instruments Incorporated
Product Folder Links: TPS2492 TPS2493