Datasheet

TPS2492

TPS2493

SLUSA65C –JULY 2010–REVISED JANUARY 2013

www.ti.com

TIMER and PG Operation (Figure 13)

The TIMER pin charges C

as long as limiting action continues, and discharges at a 1/10 charge rate when

limiting stops. If the voltage on C

reaches 4 V before the output is charged, the external FET is turned off and

either a latch-off or restart cycle commences, depending on the part type. The open-drain PG output provides a

deglitched end-of-charge indication which is based on the voltage across the external FET. PG is useful for

preventing a downstream DC-to-DC converter from starting while C

is still charging. PG goes active (low) about

9 ms after C

is charged. This delay allows the external FET to fully turn on and any transients in the power

circuits to end before the converter starts up. The resistor pull-up shown on pin PG in the Typical Application

Circuit only demonstrates operation; the actual connection to the converter depends on the application. Timing

can appear to terminate early in some designs if operation transitions out of the power limit mode into a gate

charge-rate limited mode at low V

values. This effect sometimes occurs because gate capacitances, C

and

, are nonlinear with applied voltage, getting larger at smaller voltage. This can be seen in Figure 13.

Figure 13. Basic Board Insertion

Product Folder Links: TPS2492 TPS2493