Datasheet

TPS2492

TPS2493

www.ti.com

SLUSA65C –JULY 2010–REVISED JANUARY 2013

APPLICATION INFORMATION

Basic Operation

The TPS2492/93 features include:

1. Adjustable under-voltage and over-voltage lockout;

2. Turn-on inrush limit;

3. High-side gate drive for an external N-channel FET;

4. FET protection (power limit and current limit);

5. Adjustable overload timeout;

6. Output current monitor;

7. Status output;

8. Charge-complete indicator for downstream converter sequencing; and

9. Optional automatic restart mode.

The TPS2492/93 features power-limiting FET protection that allows independent control of current limit (to set

maximum full-load current), power limit (to keep FET in its safe operating area), and overload time (to control

temperature rise). The power limiting feature controls the V and I across the FET to protect it, and does not

control load power. This protection is a specialized form of foldback output limiting. Given a constant power

dissipation, computation of peak junction temperature is straight forward. The TPS2393 provides a small

operating duty cycle into a short, reducing the average temperature rise of the FET to levels similar to normal

operation in many systems. This prevents overheating and failure with prolonged exposure to an output short.

The typical application circuit, and oscilloscope plots of Figure 13 and Figure 17 demonstrate many of the

functions described above.

Board Plug-In (Figure 13)

Only the bypass capacitor charge current and small bias currents are evident when a board is first plugged in as

seen in Figure 13. The TPS2492/93 is held inactive with GATE, PROG, and TIMER held low, and with PG and

FLT open drain, for less than 1 ms while internal voltages stabilize. Then GATE, PROG, TIMER, FLT and PG are

released and the part begins sourcing current to the GATE pin because UVEN is high and OV is low. The

external FET begins to turn on while the voltage across it, V

(SENSE-OUT)

, and current through it, V

(VCC-

SENSE)

SENSE

, are monitored. Current initially rises to the value which satisfies the power limit engine (P

LIM

/ V

VCC

)

since the output capacitor was discharged. The shape of the input current waveform shows the operation of the

FET power limit. In this case, the 5-A current limit is never reached as the output reaches full charge. This is

likely due to the limited gate slew rate.

Product Folder Links: TPS2492 TPS2493