Datasheet

EVM Assembly Drawings and Layout Guidelines

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Figure 10. Bottom Layout

6.2 Layout Guidelines

The TPS2482 and TPS2483 circuit layout should follow power and EMI, ESD best practice guidelines. A

basic set of recommendations include:

• Arrange the power devices so power flows in a sequential, linear fashion.

• The TPS2482 and TPS2483 should be placed close to the sense resistor and MOSFET using a Kelvin

type connection to achieve accurate current sensing.

• A low-impedance GND connection is required because the TPS2482 and TPS2483 can momentarily

sink upwards of 100 mA from the gate of the MOSFET. The GATE amplifier has high bandwidth while

active, so keep the GATE trace length short.

• Large copper fills and traces should be used on SMT power-dissipating devices, and wide traces or

overlay copper fills should be used in the power path.

• The PROG, TIMER, and EN pins have high input impedances; therefore, their input lead length should

be minimized.

• Oversize power traces and power device connections assuring low voltage drop and good thermal

performance.

TPS2482 and TPS2483 Evaluation Module SLVU795–November 2012

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