Datasheet

TPS2480
TPS2481
www.ti.com SLUS939B –APRIL 2010–REVISED DECEMBER 2010
Register Details
All TPS2480/81 16-bit registers are actually two 8-bit registers.
Configuration Register 00h (Read/Write)
BIT # D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
BIT
RST — BRNG PG1 PG0 BADC4 BADC3 BADC2 BADC1 SADC4 SADC3 SADC2 SADC1 MODE3 MODE2 MODE1
NAME
POR
0 0 1 1 1 0 0 1 1 0 0 1 1 1 1 1
VALUE
Bit Descriptions
RST: Reset Bit
Bit 15 Setting this bit to '1' generates a system reset that is the same as power-on reset. Resets all registers to default
values; this bit self-clears.
BRNG: Bus Voltage Range
Bit 13 0 = 16-V FSR
1 = 32-V FSR (default value)
PG: PGA (Shunt Voltage Only)
Bits 11, 12 Sets PGA gain and range. Note that the PGA defaults to ÷8 (320-mV range). Table 5 shows the gain and range for
the various product gain settings.
Table 5. PG Bit Settings
(1)
PG1 PG0 GAIN RANGE
0 0 1 ±40 mV
0 1 ÷2 ±80 mV
1 0 ÷4 ±160 mV
1 1 ÷8 ±320 mV
(1) Shaded values are default.
BADC: BADC Bus ADC Resolution/Averaging
Bits 7–10 These bits adjust the Bus ADC resolution (9-, 10-, 11-, or 12-bit) or set the number of samples used when
averaging results for the Bus Voltage Register (02h).
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