Datasheet

TPS2480
TPS2481
www.ti.com SLUS939B –APRIL 2010–REVISED DECEMBER 2010
Response to a Hard Output Short (Figure 14 and Figure 15)
Figure 14 shows the short circuit response over the full time-out period. This begins when the output voltage falls
and ends when the external FET is turned off. The external FET current is actively controlled by the power
limiting engine and gate amplifier circuit while the TIMER pin charges C
T
to the 4-V threshold. Once this
threshold is reached, the TPS2480/81 disable and latch off the external FET. The TPS2480 remains latched off
until either the input voltage drops below the UVLO threshold or EN cycles through the false (low) state. The
TPS2481 will attempt a restart after going through a timing cycle.
Figure 14. Current Limit Overview
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