Datasheet

( )
LIM
PROG
LIM
P
V
10 I
=
´
J(max) S(max)
LIM
JC(max)
T T
P
R
q
-
<
TPS2480
TPS2481
SLUS939B –APRIL 2010–REVISED DECEMBER 2010 www.ti.com
Pin Description
A0, A1: Address pins for setting the TPS2480 I
2
C address. These bits can be tied to one of four pins ( GND,
SDA, SCL, VS ) which gives a total of 16 different address as shown in Table 2.
EN: The GATE driver is enabled if the positive threshold is exceeded and the internal POR and UVLO thresholds
have been satisfied. EN can be used as a logic control input, an analog input voltage monitor as illustrated by
R1/R2 in the Functional Block Diagram, or it can be tied to VCC to always enable the TPS2480/81. The
hysteresis associated with the internal comparator makes this a stable method of detecting a low input condition
and shutting the downstream circuits off. A TPS2480 that has latched off can be reset by cycling EN below its
negative threshold and back high.
GATE: Provides the high side (above VCC) gate drive for the external FET. It is controlled by the internal gate
drive amplifier, which provides a pull-up of 22 mA from an internal charge pump and a strong pull-down to ground
of 75 mA (min). The pull-down current is a non-linear function of the amplifier overdrive; it provides small drive for
small overloads, but large overdrive for fast reaction to an output short. There is a separate pull-down of 2 mA to
shut the external FET off when EN or UVLO causes this to happen. An internal clamp protects the gate of the
external FET (to OUT) and generally eliminates the need for an external clamp in almost all cases for devices
with 20-V V
GS(max)
ratings; an external Zener may be required to protect the gate of devices with V
GS(max)
< 16 V.
A small series resistance of 10 Ω should be inserted in the gate lead if the C
ISS
of the external FET > 200 pF,
otherwise use 33 Ω for small MOSFETs. A capacitor can be connected from GATE to ground to create a slower
inrush with a constant current profile without affecting the amplifier stability. Add a series resistor of about 1 kΩ to
the gate capacitor to maintain the gate clamping and current limit response time.
GND: This pin is connected to system ground.
OUT: This input pin is used by the constant power engine and the PG comparator to measure V
DS
of the external
FET as V
(SENSE-OUT)
. Internal protection circuits leak a small current from this pin when it is low. If the load circuit
can drive OUT below ground, connect a clamp (or freewheel) diode from OUT (cathode) to GND (anode).
PG: This open-drain output is intended to interface to downstream dc/dc converters or monitoring circuits. PG
goes open-drain (high voltage with a pull-up) after V
DS
of the external FET has fallen to about 1.25 V and a 9-ms
deglitch time period has elapsed. PG is false (low or low resistance to ground) whenever EN is false, V
DS
of the
external FET is above 2.7 V, or UVLO is active. PG can also be viewed as having an input and output voltage
monitor function. The 9-ms deglitch circuit operates to filter short events that could cause PG to go inactive (low)
such as a momentary overload or input voltage step. V
PG
voltage can be greater than V
VCC
because its ESD
protection is only with respect to ground.
PROG: The voltage applied to this pin (0.4 V to 4.0 V) programs the power limit used by the constant power
engine. Normally, a resistor divider R3/R4 is connected from VREF to PROG to set the power limit according to
the following equation:
(1)
where P
LIM
is the desired power limit of the external FET and I
LIM
is the current limit setpoint (see SENSE). P
LIM
is determined by the desired thermal stress on the external FET:
(2)
where T
J(max)
is the maximum desired transient junction temperature of the external FET and T
S(max)
is the
maximum case temperature prior to a start or restart.
V
PROG
is used in conjunction with V
DS
to compute the (scaled) current, I
D_ALLOWED
, by the constant power engine.
I
D_ALLOWED
is compared by the gate amplifier to the actual I
D
, and used to generate a gate drive. If I
D
<
I
D_ALLOWED
, the amplifier turns the gate of the external FET full on because there is no overload condition;
otherwise GATE is regulated to maintain the I
D
= I
D_ALLOWED
relationship. A capacitor may be tied from PROG to
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