TPS2480 TPS2481 www.ti.com SLUS939B – APRIL 2010 – REVISED DECEMBER 2010 Positive Voltage Intelligent Protection Device Hotswap Controller and I2C Current Monitor Check for Samples: TPS2480, TPS2481 FEATURES DESCRIPTION • • • • • • The TPS2480/81 are designed to minimize inrush into applications and protect both the load and the FET from over-current or short circuit events.
TPS2480 TPS2481 SLUS939B – APRIL 2010 – REVISED DECEMBER 2010 www.ti.com DESCRIPTION (CONT.) The TPS2480 and TPS2481 monitors shunts on buses that can vary from 9 V to 26 V and with a few external components it is possible to monitor buses as high as 80 V. The monitoring circuitry uses a single 3-V to 5.5-V supply, drawing a maximum of 1 mA of supply current.
TPS2480 TPS2481 www.ti.com SLUS939B – APRIL 2010 – REVISED DECEMBER 2010 ABSOLUTE MAXIMUM RATINGS (1) (2) (3) over operating free-air temperature range (unless otherwise noted) UNIT Input voltage range, VCC, Sense, Enable, OUT -0.3 to 100 Supply voltage, VS GND - 0.3 to 6 Input voltage, common mode, VINP, VINM GND- 0.3 to + 26 Input voltage, differential, VINP, VINM -26 to + 26 Input voltage range, PROG Output voltage range, GATE, PG -0.3 to 100 Output voltage range, TIMER, VREF -0.
TPS2480 TPS2481 SLUS939B – APRIL 2010 – REVISED DECEMBER 2010 www.ti.com ELECTRICAL CHARACTERISTICS over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Supply Current (VCC) IVCC IVS VPOR Enabled VEN = Hi VSENSE = VOUT = VVCC 450 1000 Disabled VEN = Lo VSENSE = VVCC = VOUT = 0 90 250 Quiescent current operating 0.7 1.
TPS2480 TPS2481 www.ti.com SLUS939B – APRIL 2010 – REVISED DECEMBER 2010 ELECTRICAL CHARACTERISTICS (continued) over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Power Good Output (PG) IPG = 2 mA 0.1 0.25 IPG = 4 mA 0.25 0.5 1.25 1.
TPS2480 TPS2481 SLUS939B – APRIL 2010 – REVISED DECEMBER 2010 www.ti.
TPS2480 TPS2481 www.ti.com SLUS939B – APRIL 2010 – REVISED DECEMBER 2010 DEVICE INFORMATION Functional Block Diagram VINM VS 18 4 X ADC SDA 2 SCL 20 A0 Voltage Register GND 16 19 A1 4V Reference VCC 15 Constant Power Engine Enable PROG I2C Interface Current Register VINP 17 PGA 1 Power Register 8 A V(DS) Detector Charge Pump 50mV max A 2B VREF 22m A + Gate Control Amplifier B S 7 13 GATE 14V 12 OUT S I(D) Detector 11 PG Inrush complete SENSE 14 + + 8.4V/ 8.
TPS2480 TPS2481 SLUS939B – APRIL 2010 – REVISED DECEMBER 2010 www.ti.
TPS2480 TPS2481 www.ti.com SLUS939B – APRIL 2010 – REVISED DECEMBER 2010 20-Pin TSSOP SDA 1 20 A0 SDL 2 19 A1 NC 3 18 VINM VS 4 17 VINP NC 5 16 GND EN 6 15 VCC VREF 7 14 SENSE PROG 8 13 GATE TIMER 9 12 OUT GND 10 11 PG TPS2480/81 Table 1. TERMINAL FUNCTIONS FUNCTION TPS2480/81 SDA 1 I2C Data Line DESCRIPTION SCL 2 I2C Clock NC 3 Tie to GND or float VS 4 Power input to the I2C block, 3.
TPS2480 TPS2481 SLUS939B – APRIL 2010 – REVISED DECEMBER 2010 www.ti.com Pin Description A0, A1: Address pins for setting the TPS2480 I2C address. These bits can be tied to one of four pins ( GND, SDA, SCL, VS ) which gives a total of 16 different address as shown in Table 2. EN: The GATE driver is enabled if the positive threshold is exceeded and the internal POR and UVLO thresholds have been satisfied.
TPS2480 TPS2481 www.ti.com SLUS939B – APRIL 2010 – REVISED DECEMBER 2010 ground to alter the natural constant power inrush current shape. If properly designed, the effect is to cause the leading step of current in Figure 12 to look like a ramp. PROG is internally pulled to ground whenever EN, POR, or UVLO are not satisfied or the TPS2480 is latched off. This feature serves to discharge any capacitance connected to the pin. Do not apply voltages greater than 4 V to PROG.
TPS2480 TPS2481 SLUS939B – APRIL 2010 – REVISED DECEMBER 2010 www.ti.com TYPICAL CHARACTERISTICS A/D FREQUENCY RESPONSE 2.0 ADC SHUNT OFFSET vs TEMPERATURE 100 VS+ = 5V 80 1.5 320mV Range 1.0 160mV Range 40 0.5 Offset (mV) Input Currents (mA) 60 VS+ = 3V 0 VS+ = 3V 20 0 -20 80mV Range -60 -1.0 -80 VS+ = 5V -1.
TPS2480 TPS2481 www.ti.com SLUS939B – APRIL 2010 – REVISED DECEMBER 2010 TYPICAL CHARACTERISTICS (continued) INPUT CURRENTS WITH LARGE DIFFERENTIAL VOLTAGES (VIN+ at 12V, Sweep of VIN–) ACTIVE IQ vs TEMPERATURE 0 1.2 -10 1.0 -20 VS = 5V 0.8 -40 IQ (mA) Gain (dB) -30 -50 0.6 VS = 3V -60 0.4 -70 -80 0.2 -90 0 -100 10 100 1k 10k 100k 1M -40 -25 0 25 Input Frequency (Hz) 50 100 Figure 7. Figure 8. SHUTDOWN IQ vs TEMPERATURE ACTIVE IQ vs I2C CLOCK FREQUENCY 125 1.0 16 0.
TPS2480 TPS2481 SLUS939B – APRIL 2010 – REVISED DECEMBER 2010 www.ti.com APPLICATION INFORMATION Basic Operation The TPS2480/81 provides all the features needed for a positive hotswap controller. These features include: 1. Under-voltage lockout; 2. Adjustable (system-level) enable; 3. Turn-on inrush limit; 4. High-side gate drive for an external N-channel MOSFET; 5. MOSFET protection (power limit and current limit); 6. Adjustable overload timeout (also called an electronic circuit breaker); 7.
TPS2480 TPS2481 www.ti.com SLUS939B – APRIL 2010 – REVISED DECEMBER 2010 TIMER and PG Operation (Figure 12) The TIMER pin charges CT as long as limiting action continues, and discharges at a 1/10 charge rate when limiting stops. If the voltage on CT reaches 4 V before the output is charged, the external FET is turned off and either a latch-off or restart cycle commences, depending on the part type.
TPS2480 TPS2481 SLUS939B – APRIL 2010 – REVISED DECEMBER 2010 www.ti.com Action of the Constant Power Engine (Figure 13) The calculated power dissipated in the external FET, VDS x ID, is computed under the same startup conditions as Figure 12. The current of the external FET, labeled IIN, initially rises to the value that satisfies the constant power engine; in this case it is 54 W / 48 V = 1.1 A. The 54-W value is programmed into the engine by setting the PROG voltage using Equation 1.
TPS2480 TPS2481 www.ti.com SLUS939B – APRIL 2010 – REVISED DECEMBER 2010 Response to a Hard Output Short (Figure 14 and Figure 15) Figure 14 shows the short circuit response over the full time-out period. This begins when the output voltage falls and ends when the external FET is turned off. The external FET current is actively controlled by the power limiting engine and gate amplifier circuit while the TIMER pin charges CT to the 4-V threshold.
TPS2480 TPS2481 SLUS939B – APRIL 2010 – REVISED DECEMBER 2010 www.ti.com The TPS2480/81 responds rapidly to the short circuit as seen in Figure 15. The falling OUT voltage is the result of the external FET and CO currents through the short circuit impedance. The internal GATE clamp causes the GATE voltage to follow the output voltage down and subsequently limits the negative VDS to 1.2 V.
TPS2480 TPS2481 www.ti.com SLUS939B – APRIL 2010 – REVISED DECEMBER 2010 Automatic Restart (Figure 16) The TPS2481 automatically initiates a restart after a fault has caused it to turn off the external FET. Internal control circuits use CT to count 16 cycles before re-enabling the external FET. This sequence repeats if the fault persists. The TIMER has a 1:10 charge-to-discharge current ratio, and uses a 1-V lower threshold. The fault-retry duty cycle specification quantifies this behavior.
TPS2480 TPS2481 SLUS939B – APRIL 2010 – REVISED DECEMBER 2010 www.ti.com Low Voltage Application Design Example The following example illustrates the design and component selection process for a 12-V, 40-A hotswap application. Figure 17 shows the application circuit for this design example. VCC VOUT RS D1 RG CO A1 RPG 11 1kW C1 0.
TPS2480 TPS2481 www.ti.com SLUS939B – APRIL 2010 – REVISED DECEMBER 2010 1. Choose RS The following equation includes a factor of 1.2 (20%) for VSENSE and RS tolerance along with some additional margin. RS = • VSENSE 50mV = = 1.042mΩ 1.2 ´ ILIMIT 1.2 ´ 40A (5) Choose RS = 1 mΩ ILIMIT(MAX) = VSENSE( MAX ) RS = 55mV = 55 A 1mΩ (6) 2 RS Power = ILIMIT(MAX) ´ RS = 55 A2 ´ 1mW = 3.025W (7) Multiple sense resistors in parallel should be considered. 2.
TPS2480 TPS2481 SLUS939B – APRIL 2010 – REVISED DECEMBER 2010 www.ti.com 3. Choose the Power Limit PLIM and the PROG Resistors, RPROG1 and RPROG2 M1 dissipates large amounts of power during power-up or output short circuit. Power limit, PLIM should be set to prevent M1 die temperature from exceeding a short term maximum temperature, TJ(MAX2). Short term TJ(MAX2) may be set as high as 150°C while still leaving ample margin for the typical manufacturer's rating of 175°C.
TPS2480 TPS2481 www.ti.com SLUS939B – APRIL 2010 – REVISED DECEMBER 2010 4. Choose the Timer Capacitor, CT and Turn On Time The turn on time tON, represents the time it takes the circuit to charge up the output capacitance CO and load. CT programs the fault time and should be chosen so that the fault timer does not terminate prior to completion of start up. The turn on time is a function of the type of control; current limit, power limit, or dV/dt control.
TPS2480 TPS2481 SLUS939B – APRIL 2010 – REVISED DECEMBER 2010 www.ti.com Alternative Inrush Designs Gate Capacitor (dV/dt) Control The TPS2480/81 can be configured to provide a linear dV/dt turn on characteristic. The load capacitor charging current ICHARGE, is controlled by a single capacitor from the GATE terminal to ground. M1 operates as a source follower (following the gate voltage) in this implementation.
TPS2480 TPS2481 www.ti.com SLUS939B – APRIL 2010 – REVISED DECEMBER 2010 High Voltage Application Example The TPS2480/81 can be used to monitor current from a voltage source greater than 26 V by using the OPAMP circuit shown in Figure 19. M1 VIN 9V to 57V VCC VOUT RS RIN RMA C2 0.1mF D1 CO RG + D2 5.1V RMB RPG RB 1kW CVIN CG Optional : Use with dV/dt control A1 I2C Addresses 11 C1 0.
TPS2480 TPS2481 SLUS939B – APRIL 2010 – REVISED DECEMBER 2010 www.ti.com Additional Design Considerations Use of PG Use the PG pin to control and sequence a downstream DC/DC converter. If this is not done a long time delay may be needed to allow CO to fully charge before the converter starts. Output Clamp Diode Inductive loads on the output may drive the OUT pin below GND when the circuit is unplugged or during current limit.
TPS2480 TPS2481 www.ti.com SLUS939B – APRIL 2010 – REVISED DECEMBER 2010 Output Short Circuit Measurements Repeatable short-circuit testing results are difficult to obtain. The many details of source bypassing, input leads, circuit layout and component selection, output shorting method, relative location of the short, and instrumentation all contribute to varying results. The actual short itself exhibits a certain degree of randomness as it microscopically bounces and arcs.
TPS2480 TPS2481 SLUS939B – APRIL 2010 – REVISED DECEMBER 2010 www.ti.com Power, Current, and Voltage Monitoring (PIV) The TPS2480/81 digital current-shunt monitor has an I2C / SMBus-compatible interface. It provides digital current, voltage, and power readings for accurate decision-making in precisely-controlled systems. Programmable registers allow flexible configuration for measurement resolution, and continuous versus-triggered operation.
TPS2480 TPS2481 www.ti.com SLUS939B – APRIL 2010 – REVISED DECEMBER 2010 Serial Bus Address To communicate with the TPS2480/81, the master must first address slave devices via a slave address byte. The slave address byte consists of seven address bits, and a direction bit indicating the intent of executing a read or write operation. The TPS2480/81 have two address pins, A0 and A1. Table 2 describes the pin logic levels for each of the 16 possible addresses.
TPS2480 TPS2481 SLUS939B – APRIL 2010 – REVISED DECEMBER 2010 www.ti.com Writing To/Reading From The TPS2480/81 Accessing a particular register on the TPS2480/81 is accomplished by writing the appropriate value to the register pointer. Refer to Table 4 for a complete list of registers and corresponding addresses. The value for the register pointer as shown in Figure 20 is the first byte transferred after the slave address byte with the R/W bit LOW.
0 A3 A2 A1 A0 Frame 1 Two-Wire Slave Address Byte 0 (1) 1 P7 ACK By TPS2480/81 R/W 9 P6 P4 P3 P2 P1 Frame 2 Register Pointer Byte P5 1 D15 D14 ACK By TPS2480/81 P0 9 D13 Figure 20.
TPS2480 TPS2481 SLUS939B – APRIL 2010 – REVISED DECEMBER 2010 www.ti.com ALERT 1 9 1 9 SCL SDA 0 0 0 1 1 0 0 R/W Start By Master 1 0 0 A3 A2 ACK By TPS2480/81 A1 A0 0 From TPS2480/81 Frame 1 SMBus ALERT Response Address Byte Frame 2 Slave Address Byte NACK By Master Stop By Master (1) NOTE (1): The value of the Slave Address Byte is determined by the settings of the A0 and A1 pins. Refer to Table 1. Figure 22.
TPS2480 TPS2481 www.ti.com SLUS939B – APRIL 2010 – REVISED DECEMBER 2010 High-Speed I2C Mode When the bus is idle, both the SDA and SCL lines are pulled high by the pull-up devices. The master generates a start condition followed by a valid serial byte containing High-Speed (HS) master code 00001XXX. This transmission is made in fast (400 kbps) or standard (100 kbps) (F/S) mode at no more than 400 kbps.
TPS2480 TPS2481 SLUS939B – APRIL 2010 – REVISED DECEMBER 2010 www.ti.com ADC Operation The two analog inputs to the TPS2480/81, VINP and VINM, connect to a shunt resistor in the bus of interest. The TPS2480/81 is typically powered by a separate supply from 3 V to 5 .5V. The bus being sensed can vary from 0 V to 26 V. There are no special considerations for power-supply sequencing (for example, a bus voltage can be present with the supply voltage off, and vice-versa).
TPS2480 TPS2481 www.ti.com SLUS939B – APRIL 2010 – REVISED DECEMBER 2010 All current and power calculations are performed in the background and do not contribute to conversion time; conversion times shown in the Electrical Characteristics table can be used to determine the actual conversion time. Power-Down mode reduces the quiescent current and turns off current into the TPS2480/81 inputs, avoiding any supply drain. Full recovery from Power-Down requires 40 ms.
TPS2480 TPS2481 SLUS939B – APRIL 2010 – REVISED DECEMBER 2010 www.ti.com Power Measurement Current and bus voltage are converted at different points in time, depending on the resolution and averaging mode settings. For instance, when configured for 12-bit and 128 sample averaging, up to 68 ms in time between sampling these two values is possible. Again, these calculations are performed in the background and do not add to the overall conversion time.
TPS2480 TPS2481 www.ti.com SLUS939B – APRIL 2010 – REVISED DECEMBER 2010 Programming The TPS2480/81 Power Measurement Engine Calibration Register and Scaling The Calibration Register makes it possible to set the scaling of the Current and Power Registers to whatever values are most useful for a given application.
TPS2480 TPS2481 SLUS939B – APRIL 2010 – REVISED DECEMBER 2010 www.ti.com 5. Compute the Calibration Register value using Equation 33: 0.04096 Cal = trunc Current_LSB ´ R SHUNT Cal = 4096 (33) 6. Calculate the Power LSB, using Equation 34. Equation 34 shows a general formula; because the bus voltage measurement LSB is always 4 mV, the power formula reduces to the calculated result. Power_LSB = 20 ´ Current_LSB Power_LSB = 400 ´ 10-6 (34) 7.
TPS2480 TPS2481 www.ti.com SLUS939B – APRIL 2010 – REVISED DECEMBER 2010 Max_Current_Before_Overflow = 0.64 (Note: This result is displayed by software as seen in Figure 26.) Max_ShuntVoltage = Max_Current_Before_Overflow ´ RSHUNT Max_ShuntVoltage = 0.32 (36) If Max_ShuntVoltage ≥ VSHUNT_MAX Max_ShuntVoltage_Before_Overflow = VSHUNT_MAX Else Max_ShuntVoltage_Before_Overflow= Max_ShuntVoltage End If Max_ShuntVoltage_Before_Overflow = 0.32 NOTE This result is displayed by software as seen in Figure 26.
TPS2480 TPS2481 SLUS939B – APRIL 2010 – REVISED DECEMBER 2010 www.ti.com Figure 26 illustrates how to perform the same procedure discussed in this example using the automated TPS2480/81EVM software. NOTE The same numbers used in the nine-step example are used in the software example in Figure 26. Also note that Figure 26 illustrates which results correspond to which step (for example, the information entered in Step 1 is enclosed in a box in Figure 26 and labeled).
TPS2480 TPS2481 www.ti.com SLUS939B – APRIL 2010 – REVISED DECEMBER 2010 Calibration Example 2 (Overflow Possible) This design example uses the nine-step procedure for calibrating the TPS2480/81 where overflow is possible. Figure 27 illustrates how the same procedure is performed using the automated TPS2480/81EVM software. NOTE (The same numbers used in the nine-step example are used in the software example in Figure 27.
TPS2480 TPS2481 SLUS939B – APRIL 2010 – REVISED DECEMBER 2010 www.ti.com 7. Compute the maximum current and shunt voltage values (before overflow), as shown by Equation 44 and Equation 45. Note that both Equation 44 and Equation 45 involve an If - then condition. Max_Current = Current_LSB ´ 32767 Max_Current = 62.
TPS2480 TPS2481 www.ti.com SLUS939B – APRIL 2010 – REVISED DECEMBER 2010 Figure 27 illustrates how to perform the same procedure discussed in this example using the automated TPS2480/81EVM software. NOTE (The same numbers used in the nine-step example are used in the software example in Figure 27. Also note that Figure 27 illustrates which results correspond to which step (for example, the information entered in Step 1 is enclosed in a box in Figure 27 and labeled).
TPS2480 TPS2481 SLUS939B – APRIL 2010 – REVISED DECEMBER 2010 www.ti.com REGISTER INFORMATION The TPS2480/81 uses a bank of registers for holding configuration settings, measurement results, maximum/minimum limits, and status information. Table 4 summarizes the TPS2480/81 registers; illustrates registers. Register contents are updated 4 ms after completion of the write command.
TPS2480 TPS2481 www.ti.com SLUS939B – APRIL 2010 – REVISED DECEMBER 2010 Register Details All TPS2480/81 16-bit registers are actually two 8-bit registers.
TPS2480 TPS2481 SLUS939B – APRIL 2010 – REVISED DECEMBER 2010 www.ti.com SADC: SADC Shunt ADC Resolution/Averaging Bits 3–6 These bits adjust the Shunt ADC resolution (9-, 10-, 11-, or 12-bit) or set the number of samples used when averaging results for the Shunt Voltage Register (01h). BADC (Bus) and SADC (Shunt) ADC resolution/averaging and conversion time settings are shown in Table 6. Table 6.
TPS2480 TPS2481 www.ti.com SLUS939B – APRIL 2010 – REVISED DECEMBER 2010 Data Output Registers Shunt Voltage Register 01h (Read-Only) The Shunt Voltage Register stores the current shunt voltage reading, VSHUNT. Shunt Voltage Register bits are shifted according to the PGA setting selected in the Configuration Register (00h). When multiple sign bits are present, they will all be the same value. Negative numbers are represented in two's complement format.
TPS2480 TPS2481 SLUS939B – APRIL 2010 – REVISED DECEMBER 2010 www.ti.com Table 8. Shunt Voltage Register Format (1) VSHUNT Reading (mV) Decimal Value PGA = ÷ 8 (D15…..................D0) PGA = ÷ 4 (D15…..................D0) PGA = ÷ 2 (D15…..................D0) PGA = ÷ 1 (D15…..................D0) 320.02 32002 0111 1101 0000 0000 0011 1110 1000 0000 0001 1111 0100 0000 0000 1111 1010 0000 320.01 32001 0111 1101 0000 0000 0011 1110 1000 0000 0001 1111 0100 0000 0000 1111 1010 0000 320.
TPS2480 TPS2481 www.ti.com SLUS939B – APRIL 2010 – REVISED DECEMBER 2010 Bus Voltage Register 02h (Read-Only) The Bus Voltage Register stores the most recent bus voltage reading, VBUS. At full-scale range = 32 V (decimal = 8000, hex = 1F40), and LSB = 4 mV.
TPS2480 TPS2481 SLUS939B – APRIL 2010 – REVISED DECEMBER 2010 www.ti.com Current Register 04h (Read-Only) Full-scale range and LSB depend on the value entered in the Calibration Register. See the TPS2480/81 Power Measurement Engine section. Negative values are stored in two's complement format.
TPS2480 TPS2481 www.ti.com SLUS939B – APRIL 2010 – REVISED DECEMBER 2010 REVISION HISTORY Changes from Revision A (April, 2010) to Revision B Page • Changed Increased the input range from 20-V to 26-V ........................................................................................................ 1 • Changed Simplified Application Diagram drawing on the first page. ....................................................................................
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PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant TPS2480PWR TSSOP PW 20 2000 330.0 16.4 6.95 7.1 1.6 8.0 16.0 Q1 TPS2481PWR TSSOP PW 20 2000 330.0 16.4 6.95 7.1 1.6 8.0 16.
PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS2480PWR TSSOP PW 20 2000 367.0 367.0 38.0 TPS2481PWR TSSOP PW 20 2000 367.0 367.0 38.
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