Datasheet

EVM Assembly Drawing and Layout Guidelines

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Figure 11. Bottom Side Placement/Routing

6.2 Layout Guidelines

The TPS2480/1 circuit layout must follow power and EMI/ESD best-practice guidelines. A basic set of

recommendations include:

• Arrange the high-power devices so that current flows in a sequential, linear fashion.

• Place a good ground plane under the power planes and TPS2480/1.

• The TPS2480/81 must be placed close to the sense resistor and MOSFET using a Kelvin type

connection to achieve accurate current sensing.

• A low-impedance GND connection is required because the TPS2480/81 can momentarily sink upwards

of 100 mA from the gate of the MOSFET. The GATE amplifier has high bandwidth while active, so

keep the GATE trace length short.

• Spacing consistent with safety standards like IEC60950 must be observed between the 48-V input

voltage rails and between the input and an isolated converter output.

• Large copper fills and traces must be used on SMT power-dissipating devices, and wide traces or

overlay copper fills must be used in the power path.

• The PROG, TIMER, and EN pins have high input impedances; therefore, their input lead length must

be minimized.

• Oversize power traces and power device connections assuring low voltage drop and good thermal

performance.

TPS2480 and TPS2481 Evaluation Module SLUU370A–January 2010–Revised June 2010

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