Datasheet

TPS24720
www.ti.com SLVSAL1C –MARCH 2011–REVISED SEPTEMBER 2013
ADDITIONAL DESIGN CONSIDERATIONS
Use of PGb
Use the PGb pin to control and coordinate a downstream dc/dc converter. If this is not done, then a long time
delay is needed to allow C
OUT
to fully charge before the converter starts. An undesirable latch-up condition can
be created between the TPS24720 output characteristic and the dc/dc converter input characteristic if the
converter starts while C
OUT
is still charging; using the PGb pin is one way to avoid this.
Output Clamp Diode
Inductive loads on the output may drive the OUT pin below GND when the circuit is unplugged or during a
current-limit event. The OUT pin ratings can be satisfied by connecting a diode from OUT to GND. The diode
should be selected to control the negative voltage at the full short-circuit current. Schottky diodes are generally
recommended for this application.
Gate Clamp Diode
The TPS24720 has a relatively well-regulated gate voltage of 12 V–15.5 V with a supply voltage V
VCC
higher
than 4 V. A small clamp Zener from gate to source of M
1
is recommended if V
GS
of M
1
is rated below 12 V. A
series resistance of several hundred ohms or a series silicon diode is recommended to prevent the output
capacitance from discharging through the gate driver to ground.
High-Gate-Capacitance Applications
Gate voltage overstress and abnormally large fault-current spikes can be caused by large gate capacitance. An
external gate clamp Zener diode is recommended to assist the internal Zener if the total gate capacitance of M
1
exceeds about 4000 pF. When gate capacitor dV/dt control is used, a 1-kΩ resistor in series with C
GATE
is
recommended (see Figure 39). If the series R-C combination is used for MOSFETs with C
ISS
less than 3000 pF,
then a Zener is not necessary .
Bypass Capacitors
It is a good practice to provide low-impedance ceramic capacitor bypassing of the VCC and OUT pins. Values in
the range of 10 nF to 1 µF are recommended. Some system topologies are insensitive to the values of these
capacitors; however, some are not and require minimization of the value of the bypass capacitor. Input
capacitance on a plug-in board may cause a large inrush current as the capacitor charges through the low-
impedance power bus when inserted. This stresses the connector contacts and causes a short voltage sag on
the input bus. Small amounts of capacitance (e.g., 10 nF to 0.1 µF) are often tolerable in these systems.
Output Short-Circuit Measurements
Repeatable short-circuit testing results are difficult to obtain. The many details of source bypassing, input leads,
circuit layout and component selection, output shorting method, relative location of the short, and instrumentation
all contribute to variation in results. The actual short itself exhibits a certain degree of randomness as it
microscopically bounces and arcs. Care in configuration and methods must be used to obtain realistic results. Do
not expect to see waveforms exactly like those in the data sheet; every setup differs.
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