Datasheet

ISS
FLT ON
GATE
FLT
5.9 V C
t t ,
I
therefore,
5.9 V 2040 pF
t 0.614 ms 1.22 ms
20 μA
´
= +
´
= + =
ON
t =
2
OUT VCC(MAX) OUT VCC(MAX)
OUT LIM
LIM LIM VCC(MAX)
2
LIM LIM
LIM
C V C V
C P
if P I V
2 P I
2 I
´ ´
´
+ - < ´
´
´
OUT VCC(MAX)
LIM LIM VCC(MAX)
LIM
C V
if P I V
I
´
> ´
( )
( )
2
ON
2
therefore,
470 μF 12 V
470 μF 29.3 W 470 μF 12 V
t 0.614 ms
2 29.3 W 12 A
2 12 A
´
´ ´
= + - =
´
´
LIM SENSE
SNS PL _ MIN
IN _ MAX
LIM IN _ MAX
LIM FB
LIM
P R
29.3 W 2 m
V 4.19 mV (> 3 mV)
V 14 V
I V
12 A 14 V
P 5.73 (< 10)
P 29.3 W
-
-
´
´ W
= = =
´
´
= = =
TPS24720
SLVSAL1C –MARCH 2011–REVISED SEPTEMBER 2013 www.ti.com
Power limit fold back (P
LIM-FB
) is the ratio of operating current limit (I
LIM
) and minimum power limited (regulated)
current (when V
OUT
= 0 V). Degradation of programmed power limit (P
LIM
) accuracy and start up issues may
occur if P
LIM-FB
is too large. Equation 9 calculates V
SNS-PL_MIN
(minimum sense voltage during power limit) and
P
LIM-FB
. To ensure reliable operation, verify that P
LIM-FB
< 10 and V
SNS,PL,MIN
> 3 mV.
(9)
STEP 4. Choose Output Voltage Rising Time, t
ON
, and Timing Capacitor C
T
The maximum output voltage rise time, t
ON
, set by timer capacitor C
T
must suffice to fully charge the load
capacitance C
OUT
without triggering the fault circuitry. Equation 10 defines t
ON
for two possible inrush cases.
Assuming that only the load capacitance draws current during startup,
(10)
The next step is to determine the minimum fault-timer period. In Equation 10, the output rise time is t
ON
. This is
the amount of time it takes to charge the output capacitor up to the final output voltage. However, the fault timer
uses the difference between the input voltage and the gate voltage to determine if the TPS24720 is still in inrush
limit. The fault timer continues to run until V
GS
rises 5.9 V (for V
VCC
= 12 V) above the input voltage. Some
additional time must be added to the charge time to account for this additional gate voltage rise. The minimum
fault time can be calculated using Equation 11,
(11)
where C
ISS
is the MOSFET input capacitance and I
GATE
is the minimum gate sourcing current of TPS24720, or
20 μA. Using the example parameters and the CSD16403Q5 data sheet in Equation 11 leads to a minimum fault
time of 1.22 ms. This time is derived considering the tolerances of C
OUT
, C
ISS
, I
LIM
, P
LIM
, I
GATE
, and V
VCC(MAX)
.
The fault timer must be set to a value higher than 1.22 ms to avoid turning off during start-up, but lower than any
maximum fault time limit determined by the device SOA curve (see Figure 38) derated for operating junction
temperature.
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