Datasheet

TPS24720
SLVSAL1C –MARCH 2011–REVISED SEPTEMBER 2013 www.ti.com
PGb, FLTb, AND TIMER OPERATIONS
The open-drain PGb output provides a deglitched end-of-inrush indication based on the voltage across M
1
. PGb
is useful for preventing a downstream dc/dc converter from starting while its input capacitor C
OUT
is still charging.
PGb goes active-low about 3.4 ms after C
OUT
is charged. This delay allows M
1
to fully turn on and any transients
in the power circuits to end before the converter starts up. This type of sequencing prevents the downstream
converter from demanding full current before the power-limiting engine allows the MOSFET to conduct the full
current set by the current limit I
LIM
. Failure to observe this precaution may prevent the system from starting. The
pullup resistor shown on the PGb pin in the typical application diagram on the front page is illustrative only; the
actual connection to the converter depends on the application. The PGb pin may indicate that inrush has ended
before the MOSFET is fully enhanced, but the downstream capacitor will have been charged to substantially its
full operating voltage. Care should be taken to ensure that the MOSFET on-resistance is sufficiently small to
ensure that the voltage drop across this transistor is less than the minimum power-good threshold of 140 mV.
After the hot-swap circuit successfully starts up, the PGb pin can return to a high-impedance status whenever the
drain-to-source voltage of MOSFET M
1
exceeds its upper threshold of 340 mV, which presents the downstream
converters a warning flag. This flag may occur as a result of overload fault, output short fault, input overvoltage,
higher die temperature, or the GATE shutdown by UVLO, EN or ENSD.
FLTb is an indicator that the allowed fault-timer period during which the load current can exceed the programmed
current limit (but not the fast-trip threshold) expires. The fault timer starts when a current of approximately 10 μA
begins to flow into the external capacitor, C
T
, and ends when the voltage of C
T
reaches TIMER upper threshold,
i.e., 1.35 V. FLTb pulls low at the end of the fault timer. Otherwise, FLTb assumes a high-impedance state.
The fault-timer state requires an external capacitor C
T
connected between the TIMER pin and GND pin. The
duration of the fault timer is the charging time of C
T
from 0 V to its upper threshold of 1.35 V. The fault timer
begins to count under any of the following three conditions:
1. In the inrush mode, TIMER begins to source current to the timer capacitor, C
T
, when MOSFET M
1
is
enabled. TIMER begins to sink current from the timer capacitor, C
T
when V
(GATE – VCC)
exceeds the timer
activation voltage (see the Inrush Operation section). If V
(GATE – VCC)
does not reach the timer activation
voltage before TIMER reaches 1.35 V, then the TPS24720 disables the external MOSFET M
1
. After the
MOSFET turns off, the timer goes into either latch mode or retry mode, depending on the LATCH pin status.
2. In an overload fault, TIMER begins to source current to the timer capacitor, C
T
, when the load current
exceeds the programmed current limits. When the timer capacitor voltage reaches its upper threshold of
1.35 V, TIMER begins to sink current from the timer capacitor, C
T
, and the GATE pin is pulled to ground.
After the fault timer period, TIMER may go into latch mode or retry mode, depending on the LATCH pin
status.
3. In output short-circuit fault, TIMER begins to source current to the timer capacitor, C
T
, when the load current
exceeds the programmed current limits following a fast-trip shutdown of M
1
. When the timer capacitor voltage
reaches its upper threshold of 1.35 V, TIMER begins to sink current from the timer capacitor, C
T
, and the
GATE pin is pulled to ground. After the fault timer period, TIMER may go into latch mode or retry mode,
depending on the LATCH pin status.
If the fault current drops below the programmed current limit within the fault timer period, V
TIMER
decreases and
the pass MOSFET remains enabled.
The behaviors of TIMER are different in the latch mode and retry mode. If the timer capacitor reaches the upper
threshold of 1.35 V, then:
• In latch mode, the TIMER pin continues to charge and discharge the attached capacitor periodically until
TPS24720 is disabled by UVLO, EN, ENSD, or OV, as shown in Figure 36.
• In retry mode, TIMER charges and discharges C
T
between the lower threshold of 0.35 V and the upper
threshold of 1.35 V for sixteen cycles before the TPS24720 attempts to re-start. The TIMER pin is pulled to
GND at the end of the 16
th
cycle of charging and discharging and then ramps from 0 V to 1.35 V for the initial
half-cycle in which the GATE pin sources current. This periodic pattern is stopped once the overload fault is
removed or the TPS24720 is disabled by UVLO, EN, ENSD, or OV.
OVERTEMPERATURE SHUTDOWN
The TPS24720 includes a built-in overtemperature shutdown circuit designed to disable the gate driver if the die
temperature exceeds approximately 140°C. An overtemperature condition also causes the FLTb, FFLTb and
PGb pins to go to high-impedance states. Normal operation resumes once the die temperature has fallen
approximately 10°C.
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