Datasheet

TPS2420
SLUS903E –JANUARY 2009–REVISED MAY 2013 www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
PRODUCT INFORMATION
(1)
JUNCTION
DEVICE PACKAGE MARKING
TEMPERATURE
TPS2420 –40°C to 125°C RSA (4-mm × 4-mm QFN) TPS2420
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or visit the
device product folder on www.ti.com.
ABSOLUTE MAXIMUM RATINGS
(1) (2)
over operating free-air temperature range (unless otherwise noted)
VALUE UNIT
Voltage range , V
IN
, V
OUT
–0.3 to 25
V
Voltage range, FLT, PG –0.3 to 20
Output sink current, FLT, PG 10 mA
Input voltage range, EN LTCH –0.3 to 6 V
Input current (LTCH internally clamped to 3 V) LTCH = 0 V, 35 μA
Voltage range CT
(3)
, IFLT
(3)
, IMAX, IMON
(3)
, LTCH –0.3 to 3
ESD rating, HBM 2500 V
ESD rating, CDM 400
Operating junction temperature range, T
J
Internally Limited
°C
Storage temperature range, T
stg
–65 to 150
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to GND.
(3) Do not apply voltage to these pins.
DISSIPATION RATINGS
(1)
θ
JA
θ
JA
θ
JA
PACKAGE
LOW K
(2)
, °C/W HIGH K
(3)
, °C/W BEST
(4)
, °C/W
RSA 211 55 50
(1) Tested per JEDEC JESD51, natural convection. The definitions of high-k and low-k are per JESD 51-7 and JESD 51-3.
(2) Low-k (2 signal – no plane, 3-inch by 3-inch board, 0.062 inch thick, 1 oz. copper) test board with the pad soldered, and an additional
0.12 inch 2 of top-side copper added to the pad.
(3) High-k is a (2 signal – 2 plane) test board with the pad soldered.
(4) The best case thermal resistance is obtained using the recommendations per SLMA002A (2 signal – 2 plane with the pad connected to
the plane).
RECOMMENDED OPERATING CONDITIONS
PARAMETER MIN MAX UNIT
VIN, VOUT Voltage range 3 20 V
EN Voltage range 0 5 V
FLT, PG Voltage range 0 20 V
FLT, PG Output sink current 0 1 mA
LTCH Voltage range 0 3 V
CT 0.1 100 μF
T
J
Junction temperature –40 125 °C
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