Datasheet
SLUS562A − JUNE 2003 − REVISED SEPTEMBER 2003
12
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APPLICATION INFORMATION
RAMPHI
1
7
6
3
4
2
8
5
IRAMP
EN
RTN
−VIN
GATE
ISENS
FLTTIME
+
1.4 V
600 nA
SLOW
99 R
R 40 mV
ENA
+
30 V
EN_AMP
+
LCA
VDD
OC
+
100 mV
+
LATCH/
LOGIC
QS
RST
+
ENA
RTRY
4 V
0.5 V
TIMER BLOCK
DCHG
TPS2399 ONLY
OL
OVERLOAD
COMPARATOR
SQ
QR
GATEHI
ENA
FLT
OC
UDG−03068
10 µA
50 µA
0.4 µA
VDD
Ramp Control
14 V
FLT
PG
ON
Figure 19. Block Diagram
Fault timing is accomplished by connecting a capacitor between the FLTTIME and −VIN pins, allowing
user-programming of the timeout period. Whenever the hot swap controller is in current control mode as
described above, the LCA asserts an overcurrent indication (OC in the Figure 17 diagram). Overcurrent fault
timing is inhibited during the slow turn-on portion of the IRAMP waveform. However, once the device transitions
to the normal rate current ramp (V
O(IRAMP)
≥ 0.5 V), the external capacitor is charged by a 50-µA source,
generating a voltage ramp at the FLTTIME pin. If the load voltage ramps successfully, the fault capacitor is
discharged (DCHG signal), and load initialization can begin. However, if the timing capacitor voltage attains the
4-V fault threshold, the LCA is disabled, the pass FET is rapidly turned off, and the fault is latched. Fault capacitor
charging ceases, and the capacitor is then discharged. In addition, latching of a fault condition causes rapid
discharge of the IRAMP capacitor. In this manner, the soft-start function is then reset and ready for the next
output enable, if and when conditions permit.