Datasheet

TPS2394
www.ti.com SLVSAA9 –AUGUST 2010
DEVICE INFORMATION
PIN FUNCTIONS
PIN I/O DESCRIPTION
NAME NO.
FLT 2 O Open-drain, active-low indication that the part is in fault.
FLTTIM 5 I/O Connection for user programming of the fault timeout period.
GAT 11 O Gate drive for external N-channel MOSFET that ramps load current and disconnects in the event of a
fault.
NC 9 Not connected, leave floating
NC 8 Not connected, leave floating
NC 14 Not connected, leave floating
NC 13 Not connected, leave floating
OV 4 I Over voltage sense input.
PG 12 O Open-drain, active-high indication that the power MOSFET is fully enhanced.
RAMP 6 I/O Programming input for setting the inrush current slew rate.
RTN 1 I Supply return (for positive grounded system).
SENSE 10 I Positive current sense input.
SOURCE 7 I/O Negative current sense input.
UV 3 I Under voltage sense input.
PIN DESCRIPTIONS
FLT: Open-drain, active-low indication that TPS2394 has shut down due to a faulted load. This happens if the
load current stays limited by the linear current amplifier (LCA) for more than the fault time (time to charge the
FLTTIM capacitor). FLT is cleared when input supply drops below the UV-comparator threshold or exceeds the
OV-comparator threshold. The FLT output is pulled to SOURCE. The FLT output is able to sink 10 mA when in
fault, withstand 80 V without leakage when not faulted, and withstand transients as high as 100 V when limited
by a series resistor of at least 10 kΩ.
FLTTIM: Connection for user programming of the fault timeout period. An external capacitor connected from
FLTTIM to SOURCE establishes the timeout period to declare a fault condition. This timeout protects against
indefinite current sourcing into a faulted load, and also provides a filter against nuisance trips from momentary
current spikes or surges. TPS2394 defines a fault condition as voltage at the SENSE pin at or greater than the
42-mV fault threshold. When a fault condition exists, the timer is active. The devices manage fault timing by
charging the external capacitor to the 4-V fault threshold, then subsequently discharging it at approximately 1%
the charge rate to establish the duty cycle for retrying the load. Whenever the fault latch is set (timer expired),
GAT and FLT are pulled low.
GAT: Gate drive for an external N-channel protection power MOSFET. When input supply is above the UV
threshold and below the OV threshold, gate drive is enabled and the device begins charging the external
capacitor connected to RAMP. RAMP develops the reference voltage at the non-inverting input of the internal
LCA. The inverting input is connected to the current sense node, SENSE. The LCA acts to slew the pass
MOSFET gate to force the SENSE voltage to track the reference. The reference is internally clamped to 42 mV,
so the maximum current that can be sourced to the load is determined by the sense resistor value as I
MAX
≤42
mV/R
SENSE
. Once the load voltage has ramped up to the input dc potential and current demand drops off, the
LCA drives GAT 14 V above SOURCE to fully enhance the pass MOSFET, completing the low-impedance
supply return path for the load.
PG: Open-drain, active-high indication that load current is below the current limit and the power MOSFET is fully
enhanced. When commanded load current is more than the actual load current, the linear current amplifier (LCA)
will raise the power MOSFET gate voltage to fully enhance the power MOSFET. At this time, the PG output will
go high. This output can be used to enable a down-stream dc-to-dc converter. The PG output is pulled to
SOURCE and is able to sink 10 mA when in fault, withstand 80 V without leakage when power is not good, and
withstand transients as high as 100 V when limited by a series resistor of at least 10 kΩ.
Copyright © 2010, Texas Instruments Incorporated 5
Product Folder Link(s): TPS2394