Datasheet

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SLUS536C − AUGUST 2002 − REVISED AUGUST 2004
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22
APPLICATION INFORMATION
With this information, the minimum recommended value timing capacitor C
FLT
can be determined. The delay
time needed will be either t
SS
or the sum of t
SS
and t
CC
, according to the estimated time to charge the load.
Since fault timing is generated by the constant-current charging of C
FLT
, the capacitor value is determined by
equation (6) or (7).
C
FLT(min)
+
55 t
SS
3.75
C
FLT(min)
+
55
ǒ
t
SS
) t
CC
Ǔ
3.75
where:
D C
FLT(min)
is the recommended capacitor value, in microfarads
D t
SS
is the result of equation (3), in seconds
D t
CC
is the result of equation (5), in seconds
For the typical application example, with the 100-µF filter capacitor in front of the dc-to-dc converter, equations
(3) and (4) estimate the load voltage ramping to −46 V during the soft-start period. If the module should operate
down to −72-V input supply, approximately another 1.58 ms of constant-current charging may be required.
Therefore, equation (7) is used to determine C
FLT(min)
, and the result is approximately 0.1 µF.
setting the undervoltage and overvoltage thresholds
The UVLO and OVLO pins can be used to set the undervoltage (V
UV
) and overvoltage (V
OV
) thresholds of the
hot swap circuit. When the input supply is below V
UV
or above V
OV
, the GATE pin is held low, disconnecting
power from the load, and deasserting the PG output. When input voltage is within the UV/OV window, the GATE
drive is enabled, assuming all other input conditions are valid for turn-on.
Threshold hysteresis is provided via two internal sources which are switched to either pin whenever the
corresponding input level exceeds the internal 1.4-V reference. The additional bias shifts the pin voltage in
proportion to the external resistance connected to it. This small voltage shift at the device pin is gained up by
the external divider to input supply levels.
UDG−20119
R8
R2
R1 R7
GND
−48V
GND
−48V
−VIN
RTN
TPS2392/93*
UVLO
OVLO
−VIN
RTN
TPS2392/93*
UVLO
OVLO
R1
200 kΩ
1%
R2
4.99 kΩ
1%
R3
3.92 kΩ
1%
(a)
(b)
V
OV_L
+
R1 ) R2 ) R3
R3
V
REF
* I
SRC_UV
R1
V
UV_L
+
R1 ) R2 ) R3
R2 ) R3
V
REF
V
OV_L
+
R7 ) R8
R8
V
TH_OV
V
UV_L
+
R1 ) R2
R2
V
TH_UV
*Additional details omitted for clarity. See block diagram on page 15 and 16 for pinout.
Figure 28. Programming the Undervoltage and Overvoltage Thresholds
(6)
(7)