Datasheet
SLUS536C − AUGUST 2002 − REVISED AUGUST 2004
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19
DETAILED DESCRIPTION
UDG−20118
+
+
0.5V
4V
SQ
QR
FAULT
LOGIC
FLTTIME
RETRY
S
R
TPS2393 ONLY
RESET
OL
OC
ON
EN
4 µs
50 µA
0.4 µA
FAULT
See block diagram on page 15 and 16 for pinout.
Figure 27. Fault Timer Block Operation
Note that because of the timing inhibit during the initial slow ramp period, the duty cycle in practice is slightly
greater than the nominal 1% value. However, sourced current during this period peaks at only about one-eighth
the maximum limit. The duty cycle of the normal ramp and constant-current periods will be about 1%.
The fault logic within the timer block automatically manages capacitor charge and discharge rates (RESET
signal), and the operational status of other device-internal circuits (ON signal). For the TPS2393, the FAULT
output remains asserted continuously during retry mode; it is only released if the fault condition clears.