Datasheet
SLUS536C − AUGUST 2002 − REVISED AUGUST 2004
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18
DETAILED DESCRIPTION
40mV
99R
R
SLOW
600 nA
0.5 V
VLIM
EN_A
IRAMP
+
UDG−20117
10 µA
Figure 26. Ramp Generator Block Details
Note that any condition which causes turn-off of the external FET (EN_A signal goes low) also causes a rapid
discharge of the IRAMP capacitor. In this manner, the soft-start function is automatically reset by the TPS2392 and
TPS2393, and ready for the next load enable event.
Fault timer operation is further detailed in Figure 26. As described earlier, the LCA OVERCURRENT output drives
the OC input signal shown in Figure 26. Overcurrent fault timing is actually inhibited during the reduced rate (slow
turn-on) portion of the IRAMP voltage waveform. However, once the device transitions to the normal rate current ramp
(V
O(IRAMP)
≥ 0.5 V), the FLTTIME capacitor is charge by the 50-µA current source, generating a second voltage ramp
at the FLTTIME pin. This voltage is monitored by the two comparators shown in the fault timer block. If this voltage
reaches the nominal 4-V comparator threshold, the fault is latched, the GATE pin pulled low rapidly, and the FAULT
output asserted. The filtered overload signal (OL) can also set the fault latch. Once a fault is latched, capacitor
charging ceases (ON signal deasserted) and the timing capacitor is discharged.
The TPS2392 latches off in response to faults. Once a fault timeout occurs, the RESET signal turns on a large
NMOS device to rapidly discharge the external capacitor, resetting the timer for any subsequent device reset.
The TPS2392 can be reset only by cycling power to the device, or by cycling the EN input.
In response to a latched fault condition, the TPS2393 enters a fault retry mode, wherein it periodically retries
the load to test for continued existence of the fault. In this mode, the FLTTIME capacitor is discharged slowly
by a about a 0.4-µA constant-current sink. When the voltage at the FLTTIME pin decays below 0.5 V, the ON
signal once again enables the LCA and ramp generator circuits, and a normal turn-on current ramp ensues.
Again, during the load charging, the OC signal causes charging of the FLTTIME capacitor until the next delay
period elapses. The sequential charging and discharging of the FLTTIME capacitor results in a typical 1% retry
duty cycle. If the current-limit fault subsides (GATE pin drives to high-level output), the timing cap is rapidly
discharged, duty-cycle operation stops, and the fault latch is reset. For an initial latched fault that was due to
an overload condition (i.e., overload comparator response), the latching action causes charging of the timer
capacitor, with GATE output already off, to initiate fault retry timing.