Datasheet
SLUS610 − JULY 2004
16
www.ti.com
DETAILED DESCRIPTION
40mV
99R
R
SLOW
600 nA
0.5 V
VLIM
EN_A
IRAMP
+
UDG−20117
10 µA
Figure 23. Ramp Generator Block Details
Note that any condition which causes turn-off of the external FET (EN_A signal goes low) also causes a rapid
discharge of the IRAMP capacitor. In this manner, the soft-start function is automatically reset by the TPS2393A,
and ready for the next load enable event.
Fault timer operation is further detailed in Figure 26. As described earlier, the LCA OVERCURRENT output
drives the OC input signal shown in Figure 26. Overcurrent fault timing is actually inhibited during the reduced
rate (slow turn-on) portion of the IRAMP voltage waveform. However, once the device transitions to the normal
rate current ramp (V
O(IRAMP)
≥ 0.5 V), the FLTTIME capacitor is charge by the 50-µA current source, generating
a second voltage ramp at the FLTTIME pin. This voltage is monitored by the two comparators shown in the fault
timer block. If this voltage reaches the nominal 4-V comparator threshold, the fault is latched, the GATE pin
pulled low rapidly, and the FAULT
output asserted. Once a fault is latched, capacitor charging ceases (ON signal
deasserted) and the timing capacitor is discharged.
In response to a latched fault condition, the TPS2393A enters a fault retry mode, wherein it periodically retries
the load to test for continued existence of the fault. In this mode, the FLTTIME capacitor is discharged slowly
by a about a 0.4-µA constant-current sink. When the voltage at the FLTTIME pin decays below 0.5 V, the ON
signal once again enables the LCA and ramp generator circuits, and a normal turn-on current ramp ensues.
Again, during the load charging, the OC signal causes charging of the FLTTIME capacitor until the next delay
period elapses. The sequential charging and discharging of the FLTTIME capacitor results in a typical 1% retry
duty cycle. If the current-limit fault subsides (GATE pin drives to high-level output), the timing cap is rapidly
discharged (reset signal asserted), duty-cycle operation stops, and the fault latch is reset.
Note that because of the timing inhibit during the initial slow ramp period, the duty cycle in practice is slightly
greater than the nominal 1% value. However, sourced current during this period peaks at only about one-eighth
the maximum limit. The duty cycle of the normal ramp and constant-current periods will be about 1%.