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SLUS610 − JULY 2004

     

  

www.ti.com

FEATURES

Wide Input Supply Range: −20 V to −80 V

D Transient Rating to −100 V

D Insertion/Removal Detection Delay

D Extended Debounce Delay

D Programmable Current Limit

D Programmable Current Slew Rate

D Programmable UV/OV Thresholds/Hysteresis

D Open-Drain Power Good (PG) Output

D Fault Timer to Eliminate Nuisance Trips

D Open-Drain Fault Output (FAULT)

D 14-Pin TSSOP package

APPLICATIONS

−48-V Distributed Power Systems

D Central Office Switching

D Wireless Base Station

DESCRIPTION

The TPS2393A integrated circuit is a hot swap

power manager optimized for use in nominal

−48-V systems. It operates with supply voltage

ranges from −20-V to −80-V, and is rated to

withstand spikes to −100 V. In conjunction with an

external N-channel FET and sense resistor, it can

be used to enable live insertion of plug-in cards

and modules in powered systems. It provides load

current slew rate control and peak magnitude

limiting. Undervoltage and overvoltage shutdown

thresholds are easily programmed via a

three-resistor divider network. In addition, two

active-low, debounced inputs provide plug-in

insertion and removal detection. The associated

debounce delay applies to both actions. A power

good (PG

) output enables downstream

converters. The TPS2393A also provides the

basic hot swap functions of electrical isolation of

faulty cards, filtered protection against nuisance

overcurrent trips, and single-line fault reporting.

The TPS2393A periodically retries the load in the

event of a fault.

UDG−04073

BAS19

0.047 F

3.92 k

4.99 k 1%

200 k 1%

20 m

1/4, 1%

10 k

100 k

100 F

100 V

OUT

= 32.8 V

= 30.8 V

= 72.6 V

5.6 V

GATE

UVLO

INSA

INSB

FAULT

FLTTIME

OVLO

DRAINSNS

ISENS

IRAMP −VIN

RTN

TPS2393A

VOUT+

VOUT−

VIN+

VIN−

DC/DC

CONVERTER

VOUT+

VOUT−

GND

−48V

IRF530

56.2 k 1%

C2, 3900 pF

R8, 56.2 k 1%

1500 pF

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Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Summary of content (30 pages)

PAGE 1
SLUS610 − JULY 2004 FEATURES D Wide Input Supply Range: −20 V to −80 V D Transient Rating to −100 V D Insertion/Removal Detection Delay D Extended Debounce Delay D Programmable Current Limit D Programmable Current Slew Rate D Programmable UV/OV Thresholds/Hysteresis D Open-Drain Power Good (PG) Output D Fault Timer to Eliminate Nuisance Trips D Open-Drain Fault Output (FAULT) D 14-Pin TSSOP package DESCRIPTION The TPS2393A integrated circuit i
PAGE 2
SLUS610 − JULY 2004 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. ORDERING INFORMATION TA −40°C to 85°C FAULT OPERATION PACKAGE TSSOP (PW)(NO TAG) PERIODIC RETRY PART NUMBER TPS2393APW The PW package is also available taped and reeled. Add an R suffix to the device type (i.e., TPS2393APWR) for quantities of 2,500 per reel.
PAGE 3
SLUS610 − JULY 2004 ELECTRICAL CHARACTERISTICS VI(−VIN) = −48 V with respect to RTN, VI(EN) = 2.8 V, VI(INSA) = 0 V, VI(INSB) = 0 V, VI(UVLO) = 2.
PAGE 4
SLUS610 − JULY 2004 ELECTRICAL CHARACTERISTICS (continued) VI(−VIN) = −48 V with respect to RTN, VI(EN) = 2.8 V, VI(INSA) = 0 V, VI(INSB) = 0 V, VI(UVLO) = 2.5 V, VI(OVLO) = 0 V, VI(ISENS) unloaded, TA = −40°C to 85°C (unless otherwise noted) all outputs PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VOL ICHG Low-level output voltage, FLTTIME VI(EN) = 0 V VI(ISENS) = 80 mV, VO(FLTTIME) = 2 V 5 mV −55 −50 −45 µA VFLT IDSG Fault threshold voltage 3.75 4.00 4.25 V 0.38 0.
PAGE 5
SLUS610 − JULY 2004 PIN ASSIGNMENTS DRAINSNS: Sense input for monitoring the load voltage status. The DRAINSNS pin determines the load status by sensing the voltage level on the external pass FET drain. DRAINSNS must be pulled low with repect to −VIN (less than 1.35 V typically) to declare a power good condition. This corresponds to a low VDS across the FET, indicating that the load voltage has successfully ramped up to the DC input level.
PAGE 6
SLUS610 − JULY 2004 PIN ASSIGNMENTS IRAMP: Programming input for setting the inrush current slew rate. An external capacitor connected between this pin and −VIN establishes the load current slew rate whenever power to the load is enabled. The device charges the external capacitor to establish the reference input to the LCA. The closed-loop control of the LCA and pass FET acts to maintain the current sense voltage at ISENS at the reference potential.
PAGE 7
SLUS610 − JULY 2004 TYPICAL CHARACTERISTICS EN (5 V/div) EN (5 V/div) VDRAIN (20 V/div) VDRAIN (50 V/div) CONTACT BOUNCE CONTACT BOUNCE ILOAD (500 mA/div) CIRAMP = 3900 pF CFLT = 0.1 µF CLOAD = 50 µF ILOAD (500 mA/div) CLOAD = 100 µF t − Time − 2.5 ms / div t − Time − 1 ms / div Figure 1. Live Insertion Event − VIN = −48 V VDRAIN (50 V/div) Figure 2.
PAGE 8
SLUS610 − JULY 2004 TYPICAL CHARACTERISTICS VUVLO_H INSB (5 V/div.) RTN (5 V/div) RAMP (2 V/div.) Extraction Delay Insertion Delay GATE (5 V/div) CLOAD = 50 µF RLOAD = 1 kΩ VDRAIN(20V/div.) t − Time − 5 ms / div t − Time − 1 ms / div Figure 6. Insertion/Extraction Detection Figure 5. UVLO Protection, Supply Falling FAULT (50 V/div) IRAMP (2 V/div) CIRAMP = 3900 pF PG (50 V/div) CIRAMP = .022 µF CIRAMP = .056 µF CFLT = 0.33 µF CLOAD = 600 µF CIRAMP = 3900 pF CFLT = 0.
PAGE 9
SLUS610 − JULY 2004 TYPICAL CHARACTERISTICS FAULT (50 V/div) FAULT (50 V/div) CIRAMP = 3900 pF CFLT = 0.047 µF CLOAD = 100 µF PG (50 V/div) CIRAMP = 3900 pF CFLT = 0.047 µF CLOAD = 100 µF PG (50 V/div) FLTTIME (2 V/div) FLTTIME (2 V/div) VDRAIN (50 V/div) VDRAIN (50 V/div) ILOAD (1 A/div) ILOAD (1 A/div) t − Time − 50 ms / div t − Time − 1 ms / div Figure 9. Fault Recovery (Large Scale View) Figure 10.
PAGE 10
SLUS610 − JULY 2004 TYPICAL CHARACTERISTICS SUPPLY CURRENT vs AMBIENT TEMPERATURE 1500 16 VOH − Output Voltage − V ICC − Supply Current − µA 900 VRTN = 48 V 600 VRTN = 36 V 300 0 −40 −15 VRTN = 20 V 35 10 VI(ISENS) = 0 V IO(GATE) = −10 µA 15 VRTN = 80 V 1200 GATE HIGH-LEVEL OUTPUT VOLTAGE vs AMBIENT TEMPERATURE 14 VRTN = 36 V 13 12 VRTN = 20 V 11 60 10 −40 85 TA − Ambient Temperature − °C −15 10 35 60 TA − Ambient Temperature − °C Figure 13. −9.
PAGE 11
SLUS610 − JULY 2004 TYPICAL CHARACTERISTICS TIMER CHARGING CURRENT vs AMBIENT TEMPERATURE −47 440 VI(ISENS) = 80 mV VO(FLTTIME) =2V VI(ISENS) = 80 mV VO(FLTTIME) = 2 V VI(RTN) = 20 V to 80 V −48 400 VRTN = 20 V IDSG − Charging Current − nA ICHG − Charging Current − µA TIMER DISCHARGE CURRENT vs AMBIENT TEMPERATURE −49 −50 −51 VRTN = 36 V VRTN = 48 V VRTN = 80 V −52 −53 −40 −15 10 35 60 360 320 280 240 −40 85 TA − Ambient Temperature − °C Figure 17.
PAGE 12
SLUS610 − JULY 2004 TYPICAL CHARACTERISTICS UVLO PIN PULL-UP CURRENT vs AMBIENT TEMPERATURE ISRC_UV − Sourced Current − µA −9.3 VI(UVLO) = 2.5 V VI(RTN) = 20 V to 48 V −9.5 −9.7 −9.9 −10.1 −10.3 −40 −15 10 35 60 TA − Ambient Temperature − °C 85 Figure 21. DETAILED DESCRIPTION When a plug-in module or printed circuit card is inserted into a live chassis slot, discharged supply bulk capacitance on the board can draw huge transient currents from the system supplies.
PAGE 13
SLUS610 − JULY 2004 DETAILED DESCRIPTION The TPS2393A operates directly from the input supply (nominal −48 VDC) rail. The −VIN pin connects to the negative voltage rail, and the RTN pin connects to the supply return. Internal regulators convert input power to the supply levels required by the device circuitry. An input UVLO circuit holds the GATE output low until the supply voltage reaches a nominal 16-V level, regardless of the status of all other control inputs.
PAGE 14
SLUS610 − JULY 2004 DETAILED DESCRIPTION 10 A RTN 11 10 A 1.35V 13 DRAINSNS 12 PG 7 IRAMP 4 FAULT 6 FLTTIME 9 ISENS 10 GATE + + INSA 2 10 A + S Q R Q 5V + INSB FLT 3 10 A EN_A H=CLOSED UVLO 1 RAMP GENERATOR + VLIM FLT 10 A ON L=CLOSED EN OVLO 14 FAULT TIMER + OC 10 A EN 5 H=CLOSED S Q R R Q OL FT OVERLOAD OVERCURRENT 100 mV OLC + + VLIM 1.4V −VIN S LCA + EN_A 8 UDG−02116 Figure 22.
PAGE 15
SLUS610 − JULY 2004 DETAILED DESCRIPTION Current fault response timing and retry duty cycle are accomplished by the fault timer block in conjunction with an external capacitor connected between the FLTTIME and −VIN pins. Whenever the hot swap controller is in current control mode, such as during inrush limiting at insertion, or in response to excessive demand during operation of the plug-in, the LCA asserts the OVERCURRENT signal shown in Figure 24.
PAGE 16
SLUS610 − JULY 2004 DETAILED DESCRIPTION 10 µA 600 nA SLOW + 0.5 V IRAMP VLIM 99R R EN_A 40mV UDG−20117 Figure 23. Ramp Generator Block Details Note that any condition which causes turn-off of the external FET (EN_A signal goes low) also causes a rapid discharge of the IRAMP capacitor. In this manner, the soft-start function is automatically reset by the TPS2393A, and ready for the next load enable event. Fault timer operation is further detailed in Figure 26.
PAGE 17
SLUS610 − JULY 2004 DETAILED DESCRIPTION OL 4 s 50 A OC 4 4V S S Q R Q FAULT + FLTTIME 6 RETRY 0.4 A ON + 0.5V RESET FAULT LOGIC R EN UDG−20118 Figure 24. Fault Timer Block Operation The fault logic within the timer block automatically manages capacitor charge and discharge rates (RESET signal), and the operational status of other device-internal circuits (ON signal).
PAGE 18
SLUS610 − JULY 2004 APPLICATION INFORMATION Setting the Sense Resistor Value Due to the current−limiting action of the internal LCA, the maximum allowable load current for an implementation is easily programmed by selecting the appropriate sense resistor value. The LCA acts to limit the sense voltage VI(ISENS) to its internal reference. Once the voltage at the IRAMP pin exceeds approximately 4 V, this limit is the clamp voltage, VREF_K.
PAGE 19
SLUS610 − JULY 2004 APPLICATION INFORMATION Setting the Fault Timing Capacitor The fault timeout period is established by the value of the capacitor connected to the FLTTIME pin, CFLT. The timeout period permits riding out spurious current glitches and surges that may occur during operation of the system, and prevents indefinite sourcing into faulted loads swapped into a live system.
PAGE 20
SLUS610 − JULY 2004 APPLICATION INFORMATION If the result of equation (4) is larger than the maximum input supply value, then the load can be expected to charge completely during the inrush slewing portion of the insertion event. However, if this voltage is less than the maximum supply input, VIN(max), the HSPM transitions to the constant-current charging of the load. The remaining amount of time required at IMAX is determined from equation (5).
PAGE 21
SLUS610 − JULY 2004 APPLICATION INFORMATION Setting the Undervoltage and Overvoltage Thresholds The UVLO and OVLO pins can be used to set the undervoltage (VUV) and overvoltage (VOV) thresholds of the hot swap circuit. When the input supply is below VUV or above VOV, the GATE pin is held low, disconnecting power from the load, and deasserting the PG output. When input voltage is within the UV/OV window, the GATE drive is enabled, assuming all other input conditions are valid for turn-on.
PAGE 22
SLUS610 − JULY 2004 APPLICATION INFORMATION For example, assume the typical application design targets have been set to undervoltage turn-on at 33 V (input supply rising), turn-off at 31 V (input voltage falling), and overvoltage shutdown at 72 V. Then equation (9) yields R1 = 200 kΩ for the 2-V hysteresis. Once the value of R1 is selected, it is used to calculate resistors R2 and R3. R2 + R3 + ȱ V UV_L 1* ȧ ǒVUV_L * 1.4Ǔ Ȳ ǒVOV_L ) 10*5 1.4 ȳ ȧ R1Ǔȴ R1 1.4 R1 V UV_L ǒVUV_L * 1.
PAGE 23
SLUS610 − JULY 2004 APPLICATION INFORMATION Using the PG Output The PG output is an indication of the load power status. PG is asserted after a load turn-on, once the load voltage has ramped up to the input dc level, as indicated by a small VDS drop across the pass FET. The load voltage is sensed by the DRAINSNS pin, which is connected to the pass FET drain through a small-signal blocking diode.
PAGE 24
SLUS610 − JULY 2004 APPLICATION INFORMATION If the selected converter cannot tolerate any voltage excursions below VIN− potential, an alternative is to drive the enable through an optocoupler. An implementation is shown in Figure 29. DC/DC CONVERTER VIN+ VOUT+ GND VDD R7 CIN 11 EN VIN− RTN PG TPS2393A* 10 µA VOUT− 12 D1 BAS19 DRNSNS 13 Q1 GATE 10 −VIN ISENS 9 8 RSENSE −48 V *Additional details omitted for clarity. Figure 27. PG Driving An Optocoupler 24 www.ti.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device TPS2393APWR Package Package Pins Type Drawing TSSOP PW 14 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 2000 330.0 12.4 Pack Materials-Page 1 6.9 B0 (mm) K0 (mm) P1 (mm) 5.6 1.6 8.0 W Pin1 (mm) Quadrant 12.
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PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS2393APWR TSSOP PW 14 2000 367.0 367.0 35.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.