Datasheet

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SLUS471D − JUNE 2002 − REVISED JANUARY 2008
12
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APPLICATION INFORMATION
In response to a latched fault condition, the TPS2391 enters a fault retry mode, wherein it periodically retries
the load to test for continued existence of the fault. In this mode, the FLTTIME capacitor is discharged slowly
by a about a 0.4-µA constant-current sink. When the voltage at the FLTTIME pin decays below 0.5 V, the LCA
and RAMP CONTROL circuits are re-enabled, and a normal turn-on current ramp ensues. Again, during the
load charging, the OC signal causes charging of the FLTTIME capacitor until the next delay period elapses. The
sequential charging and discharging of the FLTTIME capacitor results in a typical 1% retry duty cycle. If the fault
subsides (GATE pin drives to high-level output), the timing capacitor is rapidly discharged, duty-cycle operation
stops, and the fault latch is reset.
Note that because of the timing inhibit during the initial slow ramp period, the duty cycle in practice is slightly
greater than the nominal 1% value. However, sourced current during this period peaks at only about one-eighth
the maximum limit. The duty cycle of the normal ramp and constant-current periods is approximately 1%.
The FAULT LOGIC within the TIMER BLOCK automatically manages capacitor charge and discharge rates
(DCHG signal), and the enabling of the GATE output (ON signal). For the TPS2391, the FAULT
output remains
asserted continuously during retry mode; it is only released if the fault condition clears.
These hot swap controllers contain an OVERLOAD COMPARATOR which also monitors the ISENS voltage.
If sense voltage excursions above 100 mV are detected, the fault is latched, LCA disabled, and the FET gate
is rapidly pulled down, bypassing the fault timer. The timer block does apply a 4-µs deglitch filter to the OL signal
to help reduce nuisance trips. As with overcurrent faults, the TPS2390 latches the output off. For the TPS2391,
an overload fault causes charging of the timer capacitor, to initiate fault retry timing.
setting the sense resistor value
Due to the current-limiting action of the internal LCA, the maximum allowable load current for an implementation
is easily programmed by selecting the appropriate sense resistor value. The LCA acts to limit the sense voltage
V
I
(ISENS) to its internal reference. Once the voltage at the IRAMP pin exceeds approximately 4 V, this limit is
the clamp voltage, V
REF_K
. Therefore, a maximum sense resistor value can be determined from equation (1).
R
SENSE
v
33 mV
IMAX
where:
• R
SENSE
is the resistor value, and
• IMAX is the desired current limit.
(1)