Datasheet
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TPS2384
SLUS634D – NOVEMBER 2004 – REVISED MARCH 2007
TERMINAL FUNCTIONS (continued)
TERMINAL
NO. I/O DESCRIPTION
NAME
PAP PDJ
Analog Signals
This is a dual-purpose pin. When tied to an external capacitor this pin sets the internal clock. When
the CT pin is grounded the SYN pin turns from a output to an input (see SYN pin description).
The timing capacitor and the resistor on the RBIAS pin sets the internal clock frequency of the
CT 53 12 I
device. This internal clock is used for the internal state machine, integrating A/D counters, POR time
out, faults and delay timers of each port. Using a 220-pF capacitor for CT and a 124-k Ω resistor for
RBIAS sets the internal clock to 245 kHz and ensure IEEE 802.3af compliance along with maximizing
the rejection of 60-Hz line frequency noise from A/D measurements.
Bias set resistor. This resistor sets all precision bias currents within the chip. This pin will regulate to
1.25V (V2.5/2) when a resistor is connected between RBIAS and RG. This voltage and RBIAS
generate a current which is replicated and used throughout the chip. This resistor also works in
RBIAS 55 10 I
conjunction with the capacitors on CT and CINT to set internal timing values. The RBIAS resistor
should be connected RG. RBIAS is a high impedance input and care needs to be taken to avoid
signal injection from the SYN pin or I
2
C signals.
This is a dual purpose pin. When the CT pin is connected to a timing capacitor this output pin is a 0
V to 3.3V pulse of the internal clock which can be used to drive other TPS2384 SYN pins for
SYN 52 13 I/O
elimination of a timing capacitor. When the CT pin is grounded this pin becomes an input pin that can
be driven from a master TPS2384 or any other clock generator signal.
AC_LO 51 14 O Totem-pole output pin for AC Disconnect excitation.
AC_HI 50 15 O Totem-pole output pin for AC Disconnect excitation.
Digital Signals
SCL 25 40 I Serial clock input pin for the I
2
C interface.
Serial data input pin for the I
2
C interface. When tied to the SDA_O pin, this connection becomes the
SDA_I 26 39 I
standard bi-directional serial data line (SDA)
Serial data open drain output for the I
2
C interface. When tied to the SDA_I pin, this connection
SDA_O 27 38 O becomes the standard bi-directional serial data line (SDA). This is a open drain output that can
directly drive opto-coupler.
The WD_DIS pin disables the watchdog timer function when connected to 3.3 V. The pin has internal
WD_DIS 22 43 I 50-k Ω resistor to digital ground. The watchdog timer monitors the I
2
C clock pin (SCL) and the internal
oscillator activity in power management mode and only the internal oscillator activity in auto mode.
INTB 20 45 O This is an open-drain output that goes low if a fault condition occurs on any of the 4 ports.
When this input is set to logic low there is no back-off time after a discovery failure. When this pin set
ALTA/B 21 44 I to a logic high there is a back-off time (approximately 2 seconds) before initiating another discovery
cycle. This pin has an internal 50-k Ω resistor pull-down to digital ground.
A1 28 37 I
A2 29 36 I
Address 1 through 5 These are the I
2
C address select inputs. Select the appropriate binary address
A3 30 35 I on these pins by connecting to chip ground for a logic low or tying to the V3.3 pin for a logic high.
Each address line has an internal current source pull-down to digital ground.
A4 31 34 I
A5 32 33 I
The MS pin selects either the auto mode (MS low) or the power management mode, PMM, (MS
high). This pin can be held low for controller-less standalone applications. When MS is low and the
MS 63 2 I POR timing cycle is complete the chip will sequentially Discover, Classify and Power on each port.
When MS is set high the ports are controlled by register setting via the I
2
C bus. The MS pin has an
internal 50-k Ω resistor pull-down to analog ground.
This pin can be used to override the internal POR. When held low, the I
2
C interface, all the state
machines, and registers are held in reset. When all internal and external supplies are within
specification, and this pin is set to a logic high level, the POR delay will begin. The I
2
C interface and
PORB 62 3 I
registers will become active within 70 µ s of this event and communications to read or preset registers
can begin. The reset delay for the remainder of the chip then extinguishes in 1 second. This pin has
an internal 50-k Ω resistor pull-down to analog ground.
8
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