Datasheet

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TPS2384
SLUS634D – NOVEMBER 2004 – REVISED MARCH 2007
TERMINAL FUNCTIONS
TERMINAL
NO. I/O DESCRIPTION
NAME
PAP PDJ
Power and Ground
48-V input to the device. This supply can have a range of 44 to 57 V. This pin should be decoupled
V48 60 5 I
with a 0.1- µ F capacitor from V48 to AG1 placed as close to the device as possible.
10-V analog supply. The 10-V reference is generated internally and connects to the main internal
V10 58 7 O analog power bus. A 0.1- µ F de-coupling capacitor should terminate as close to this node and the
AG1 pin as possible. Do not use for an external supply.
6.3-V analog supply. A 0.1- µ F de-coupling capacitor should terminate as close to this pin and the
V6.3 59 6 O
AG1 pin as possible. Do not use for an external supply.
3.3-V logic supply. The 3.3-V supply is generated internally and connects to the internal logic power
V3.3 24 41 O bus. A 0.1- µ ìF de-coupling capacitor should terminate as close to this node and the DG pin as
possible. This output can be used as a low current supply to external logic.
2.5-V reference supply. The V2.5 is generated internally and connects to the internal reference power
V2.5 54 11 O bus. This pin should not be tied to any external supplies. A 0.1- µ F de-coupling capacitor should
terminate as close to this node and the RG pin as possible. Do not use for an external supply.
Analog ground 1. This is the analog ground of the V6.3, V10 and V48 power systems. It should be
AG1 57 8 GND externally tied to the common copper 48-V return plane. This pin should carry the low side of three
de-coupling capacitors tied to V48, V10 and V6.3.
Analog ground 2. This is the analog ground which ties to the substrate and ESD structures of the
AG2 61 4 GND device. It should be externally tied to the common copper 48-V return plane. AG1 and AG2 must be
tied together directly for the best noise immunity.
Digital ground. This pin connects to the internal logic ground bus. It should be externally tied to the
DG 23 42 GND
common copper 48-V return plane.
Reference ground. This is a precision sense of the external ground plane. The integration capacitor
(CINT) and the biasing resistor (RBIAS pin) should be tied to this ground. This ground should also be
RG 56 9 GND
used to form a printed wiring board ground guard ring around the active node of the integration
capacitor (CINT). It should tie to common copper 48-V return plane.
Port Analog Signal
P1 7 58 I
Port Positive. 48-V load sense pin. Terminal voltage is monitored and controlled differentially with
P2 10 55 I
respect to each Port N pin. Optionally, if the application warrants, this high-side path can be
P3 39 26 I
protected with the use of a self-resetting poly fuse.
P4 42 23 I
N1 6 59 I
N2 11 54 I
Port negative. 48-V load return pin. The low side of the load is switched and protected by internal
circuitry that limits the current.
N3 38 27 I
N4 43 22 I
RET1 5 60 I
RET2 12 53 I
48 V return pin.
RET3 37 28 I
RET4 44 21 I
CINT1 4 61 I
Integration capacitor This capacitor is used for the ramp A/D converter signal integration. Connect A
CINT2 13 52 I
0.027- µ F capacitor from this pin to RG. To minimize errors use a polycarbonate, poly-polypropylene,
polystyrene or teflon capacitor type to prevent leakage. Other types of capacitors can be used with
CINT3 36 29 I
increased conversion error.
CINT4 45 20 I
7
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