Datasheet

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Chip Addressing

Port/Register Cycle

Data Write Cycle

Data Read Cycle

TPS2384

SLUS634D – NOVEMBER 2004 – REVISED MARCH 2007

Table 1 shows the bit assignments during the addressing cycle.

Table 1. Address Selection Field

BIT FUNCTION

A7 Future expansion (value not compared)

A6 Future expansion (value not compared)

A5 Device address. Compared with pin A5

A4 Device address. Compared with pin A4

A3 Device address. Compared with pin A3

A2 Device address. Compared with pin A2

A1 Device address LSB. Compared with pin A1

A0 Read/Write

After the chip address cycle, the TPS2384 accepts eight bits of port/register select data as defined in Table 2 .

The SCL line high-to-low transition after the eighth data bit then latches the selection of the appropriate internal

the SDA_O line low for one clock cycle, for the acknowledge pulse.

For a data write sequence, after the Port/Register address cycle, the TPS2384 accepts the eight bits of data as

defined in the tables below. The data is latched into the previously selectedWrite Register, and the TPS2384

generates a data acknowledge pulse by pulling the SDA_O line low for one clock cycle. Common register

functions act on all ports simultaneously. Per port registers are specific to the target port only.

To reset the interface, the host or master subsequently generates a stop bit by releasing the SDA_I line during

the clock-high portion of an SCL pulse.

For a data read sequence, after the register acknowledge bit, themaster device generates a stop condition. This

is followed by a second start condition, and retransmitting the device address as described in chip address

above. For this cycle, however, the R/W bit is set to a 1 to signal the read operation. The TPS2384 again

responds with an acknowledge pulse. The address acknowledge is then followed by sequentially presenting

each of the eight data bits on the SDA_O line (MSB first), to be read by the host device on the rising edges of

SCL. After eight bits are transmitted, the host acknowledges by pulling the SDA_I line high for one clock pulse.

The completed data transfer is terminated with the host generating a stop condition.

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