Datasheet

www.ti.com
Start/Stop
Chip Address
SCL
SDA
Clock Data 1 Value Clock Data 1 Value Clock Data 0 Value Clock Data 1 Value
Write Cycle
SDA_I
ReadCycle
SDA_O
A7 A6 A5 A4 A3 A2 A1 A0 D7 R3 R2 R1 R0 D2 P1 P0 D7 D6 D5 D4 D3 D2 D1 D0
A7 A6 A5 A4 A3 A2 A1 A0 D7 R3 R2 R1 R0 D2 P1 P0 A7 A6 A5 A4 A3 A2 A1 A0
D7 D6 D5 D4 D3 D2 D1 D0
Start Bit
DeviceAddress
R/W=0
R/W
Bit
Register/Port
Address
Data from
Master to
TPS2384
Stop Bit
R/W
Bit
Start Bit
DeviceAddress
R/W=0
Register/Port
Address
DeviceAddress
R/W=1
R/W
Bit
Data from
TPS2384to
Master
Stop Bit
Start Bit
Ack Bit
Ack Bit Ack Bit
Ack Bit Ack Bit Ack Bit
Ack Bit
START/STOP SEQUENCE
STOP
CONDITION(P)
START
CONDITION(S)
SDA_O
SDA_I
TPS2384
SLUS634D – NOVEMBER 2004 – REVISED MARCH 2007
The high-to-low transition of SDA_I while SCL is high defines the start condition. The low to high transition of
SDA_I while SCL is high defines the stop condition. The master device initiates all start and stop conditions.
The first serial packet is enclosed within start and stop bits, consists of a 7-bit address field, read/write bit, and
the acknowledge bit. The acknowledge bit is always generated by the device receiving the address or data field.
Five of the seven address bits are used by the TPS2384. The value of the sixth and seventh bit is ignored and
not used by the TPS2384.
The address field of the TPS2384 is 8 bits long and contains 5 bits of device address select and a read/write bit
as and two spare bits per Table 1 . The leading two bits are not used and are reserved for future port expansion.
The five device address select bits follow this plan. These bits are compared against the hard-wired state of the
corresponding device address select pins (A1–A5). When the field contents are equivalent to the pin logic
states, the device is addressed. These bits are followed by LSB bit, which is used to set the read or write
condition (1 for read and 0 for write). Following a start condition and an address field, the TPS2384 responds
with an acknowledge by pulling the SDA_O line low during the 9
th
clock cycle if the address field is equivalent to
the value programmed by the pins. The SDA_O line remains a stable low while the 9
th
clock pulse is high.
Figure 16. I
2
C Read/Write Cycles
29
Submit Documentation Feedback