TPS2384 www.ti.com SLUS634D – NOVEMBER 2004 – REVISED MARCH 2007 QUAD INTEGRATED POWER SOURCING EQUIPMENT POWER MANAGER FEATURES APPLICATIONS • • • • • • • • • • • • • • • • • • • Quad-Port Power Management With Integrated Switches and Sense Resistors Compliant to IEEE 802.
TPS2384 www.ti.com SLUS634D – NOVEMBER 2004 – REVISED MARCH 2007 DESCRIPTION (CONTINUED) The TPS2384 has three internal supply buses (10 V, 6.3 V and 3.3 V) generated from the 48-V input supply. These supplies are used to bias all internal digital and analog circuitry. Each supply has been brought out separately for proper bypassing to insure high performance. The digital supply (3.3 V) is available for powering external loads up to 2 mA.
TPS2384 www.ti.com SLUS634D – NOVEMBER 2004 – REVISED MARCH 2007 ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) (1) (2) VALUE 100 µA V3.3 current sourced 5 mA Applied voltage on CINT#, CT, RBIAS –0.5 to 10 Applied voltage on SCL_I, SDA_I, SDA_O, INTB, A1, A2, A3, A4, A5, MS, PORB, WD_DIS, ALT_A/B, AC_LO, AC_HI –0.5 to 6 Applied voltage on V48, P#, N# –0.
TPS2384 www.ti.com SLUS634D – NOVEMBER 2004 – REVISED MARCH 2007 ELECTRICAL CHARACTERISTICS (continued) V48 = 48 V, RT = 124 kΩ, CT = 220 pF, CINT = 0.
TPS2384 www.ti.com SLUS634D – NOVEMBER 2004 – REVISED MARCH 2007 ELECTRICAL CHARACTERISTICS (continued) V48 = 48 V, RT = 124 kΩ, CT = 220 pF, CINT = 0.027 µF (low leakage), –40°C to 125°C and TA = TJ (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Port Disable Mode Port N voltage P = 48 V 47 V AC LO and AC HI Specification AC_LO, AC_HI – low output voltage 0 0.5 AC_LO – high output voltage 3.0 5.0 AC_HI – high output voltage 5.0 7.
TPS2384 www.ti.
TPS2384 www.ti.com SLUS634D – NOVEMBER 2004 – REVISED MARCH 2007 TERMINAL FUNCTIONS TERMINAL NAME NO. PAP I/O DESCRIPTION PDJ Power and Ground V48 60 5 I 48-V input to the device. This supply can have a range of 44 to 57 V. This pin should be decoupled with a 0.1-µF capacitor from V48 to AG1 placed as close to the device as possible. V10 58 7 O 10-V analog supply. The 10-V reference is generated internally and connects to the main internal analog power bus. A 0.
TPS2384 www.ti.com SLUS634D – NOVEMBER 2004 – REVISED MARCH 2007 TERMINAL FUNCTIONS (continued) TERMINAL NAME NO. PAP I/O DESCRIPTION PDJ Analog Signals This is a dual-purpose pin. When tied to an external capacitor this pin sets the internal clock. When the CT pin is grounded the SYN pin turns from a output to an input (see SYN pin description). CT 53 12 I The timing capacitor and the resistor on the RBIAS pin sets the internal clock frequency of the device.
TPS2384 www.ti.com SLUS634D – NOVEMBER 2004 – REVISED MARCH 2007 CONNECTION DIAGRAM TPS2384 64 Pin Power Pad TQFP_PAP (1) NIC = No internal connection. Pins are floating. (2) NIC pins can be tied to the ground plane for improved thermal characteristics and to prevent noise injection from unused pins. (3) NIC pins next to CINT pins should be tied to ground to prevent noise injection into A/D converter.
TPS2384 www.ti.com SLUS634D – NOVEMBER 2004 – REVISED MARCH 2007 POWERPAD OUTLINE LASER MARKER PIN 1 IDENTIFIER TOP VIEW TPS2384 64 PIN POWER PAD UP TQFP - PJD 10 (1) NIC = No internal connection. Pins are floating. (2) NIC pins can be tied to the ground plane for improved thermal characteristics and to prevent noise injection from unused pins. (3) NIC pins next to CINT pins should be tied to ground to prevent noise injection into A/D converter.
TPS2384 www.ti.com SLUS634D – NOVEMBER 2004 – REVISED MARCH 2007 AUTO MODE FUNCTIONAL DESCRIPTION Auto Mode Auto mode (AM, MS = 0) operation is the basic approach for applying power to IEEE compliant PD’s. When AM has been selected the TPS2384 automatically performs the following functions: • Discovery of IEEE 802.
TPS2384 www.ti.com SLUS634D – NOVEMBER 2004 – REVISED MARCH 2007 AUTO MODE FUNCTIONAL DESCRIPTION (continued) Auto Mode Functional Description Update Class Register PortPwr Update Reg OVI = Over Current Fault U/O V = Under or Over Voltage Fault TSD = Thermal Shutdown Fault TMPDO = PD Maintain Power Dropout Time Limit TED = Error Delay Timing A2D V/I Measurements Figure 1.
TPS2384 www.ti.com SLUS634D – NOVEMBER 2004 – REVISED MARCH 2007 AUTO MODE FUNCTIONAL DESCRIPTION (continued) AM Discovery The TPS2384 uses a four-point measurment technique using two low level probe signals (typically 4.4 V and 8.8 V) during the discovery process to determine whether a valid PD is present. The use of a multipoint detection method for the PD resistor measurement allows accurate detection even when series steering diodes are present.
TPS2384 www.ti.com SLUS634D – NOVEMBER 2004 – REVISED MARCH 2007 AUTO MODE FUNCTIONAL DESCRIPTION (continued) AM Classification After a successful discovery of a valid PD theTPS2384 enters the classification function that identifies the power level based on the PD's current signature. The classification current level is measured at a reduced terminal voltage of 17.5 V.
TPS2384 www.ti.com SLUS634D – NOVEMBER 2004 – REVISED MARCH 2007 AUTO MODE FUNCTIONAL DESCRIPTION (continued) Upon completion of classification the port classification register is updated. In AM mode this information is not used but for semi-auto mode the class information can be used for power management. Figure 4 shows actual class currents and the class assignment which were stored in the register. These assignments are compliant with the IEEE 802.
TPS2384 www.ti.com SLUS634D – NOVEMBER 2004 – REVISED MARCH 2007 AUTO MODE FUNCTIONAL DESCRIPTION (continued) AM Power Delivery After successfully discovery and classification of a valid PD the power is delivered by controlling the current to the PD until its current requirements are met or until the internal current limit is reached (approximately 425 mA). The power switch is fully enhanced after 500 µs.
TPS2384 www.ti.com SLUS634D – NOVEMBER 2004 – REVISED MARCH 2007 AUTO MODE FUNCTIONAL DESCRIPTION (continued) Over/Under Voltage Fault Over/under voltage faults are only processed after port powerup has completed (voltage/power ramp to PD is done). The TPS2384 measures the voltage between the P and N pin and if this voltage drops below the under voltage threshold (typically 43 V) or increases above the over voltage threshold (typically 55 V) the voltage timer is turned on.
TPS2384 www.ti.com SLUS634D – NOVEMBER 2004 – REVISED MARCH 2007 AUTO MODE FUNCTIONAL DESCRIPTION (continued) Over Current or Current Limit Faults Over current or current limit faults are conditions when the load current that is being sensed trips either the ICUT comparator (350 mA to 400 mA) or the ILIM comparator (400 mA to 450 mA) and turns on the current fault timer.
TPS2384 www.ti.com SLUS634D – NOVEMBER 2004 – REVISED MARCH 2007 AUTO MODE FUNCTIONAL DESCRIPTION (continued) Under Current Fault (DC Modulated Disconnect) Under current fault (dc modulated disconnect) is a condition when the load current that is being measured drops below 7.5 mA and turns on the disconnect timer.
TPS2384 www.ti.com SLUS634D – NOVEMBER 2004 – REVISED MARCH 2007 POWER MANAGEMENT MODE FUNCTIONAL DESCRIPTION Power Management Mode (PMM) Power management mode (PMM) has been designed to work efficiently with simple low-cost microcontrollers such as those in the MSP430 family. The power management mode uses 13 self-contained functions to completely control the device operation. You simply write/read through the I2C pins and wait for the function done bit to be set.
Wait for Next Function Call Set Done Bit Submit Documentation Feedback Set Done Bit Wait for Next Function Call Set Done Bit Store Value Discovery I Reg Store Value Discovery I Reg Wait for Next Function Call 4 ms Delay Start A2D Measure Chnl I (18mS) 4mSDelay Start A2D Measure Chnl I (18mS) Apply 8.8V (Imax5mA) To Chnl Apply 4.
TPS2384 www.ti.com SLUS634D – NOVEMBER 2004 – REVISED MARCH 2007 POWER MANAGEMENT MODE FUNCTIONAL DESCRIPTION (continued) PMM Discovery 1 PMM Discovery 1 function waveforms for the N and CINT pins are shown in Figure 10. The measurement is being performed using 25-kΩ impedance between the P and N pin. The Discovery 1 voltage is allowed to settle for approximately 5 ms before the A/D begins integrating. The voltage on the CINT pin shows the A/D cycle.
TPS2384 www.ti.com SLUS634D – NOVEMBER 2004 – REVISED MARCH 2007 POWER MANAGEMENT MODE FUNCTIONAL DESCRIPTION (continued) PMM Discovery 2 PMM Discovery 2 function waveforms for the N and CINT pins are shown in Figure 11. Again the measurement is being performed using 25 kΩ impedance between the P and N pin. The Discovery 2 function was called after a Discovery 1 function so the voltage ramps from 4.4 V to 8.8 V below the P pin.
TPS2384 www.ti.com SLUS634D – NOVEMBER 2004 – REVISED MARCH 2007 POWER MANAGEMENT MODE FUNCTIONAL DESCRIPTION (continued) PMM Classification PMM Classification function looks similar to Discovery 1 and 2 except that the voltage between the P and N pins regulates to approximately 17.5 V. At the end of the A/D cycle the classification current is stored in the Port Current Register and the done bit is set. The applied classification level remains until a new function is called.
TPS2384 www.ti.com SLUS634D – NOVEMBER 2004 – REVISED MARCH 2007 POWER MANAGEMENT MODE FUNCTIONAL DESCRIPTION (continued) PMM Rup Pwru PMM Rup Pwr function turns on the port power by ramping up the current that is being delivered to the load in a controlled fashion. The output current ramps from 0 mA to ILIM (typically 425 mA) in approximately 500 µs. Figure 14 shows the output voltage and current turning on for a 250-mA load. Figure 14.
TPS2384 www.ti.com SLUS634D – NOVEMBER 2004 – REVISED MARCH 2007 POWER MANAGEMENT MODE FUNCTIONAL DESCRIPTION (continued) PMM RDWN PMM RDWN function turns off the port power by ramping down the current in a controlled fashion. The output current ramps from ILIM (typically 425 mA) to 0 mA in approximately 300 µs. Figure 15 shows the output voltage and current shutting down for a 250-mA load. t - Time - 100 ms/div Figure 15.
TPS2384 www.ti.com SLUS634D – NOVEMBER 2004 – REVISED MARCH 2007 MISCELLANEOUS FUNCTIONAL DESCRIPTION PMM Faults PMM faults are the same as those shown in the AM Faults and INTB Output section. In PM mode, the port under- and overvoltage and under-current faults can be disabled by writing to the control bits in the appropriate register. Monitoring for these fault conditions is enabled by default after device POR or other reset operation.
TPS2384 www.ti.com SLUS634D – NOVEMBER 2004 – REVISED MARCH 2007 I2C Interface Description The serial interface used in the TPS2384 is a standard 2-wire I2C slave architecture. The standard SDA line of the I2C architecture is broken out into independent input and output data paths. This feature simplifies earth grounded controller applications that require opto-isolators to keep the 48-V return of the Ethernet power system floating.
TPS2384 www.ti.com SLUS634D – NOVEMBER 2004 – REVISED MARCH 2007 Start/Stop The high-to-low transition of SDA_I while SCL is high defines the start condition. The low to high transition of SDA_I while SCL is high defines the stop condition. The master device initiates all start and stop conditions. The first serial packet is enclosed within start and stop bits, consists of a 7-bit address field, read/write bit, and the acknowledge bit.
TPS2384 www.ti.com SLUS634D – NOVEMBER 2004 – REVISED MARCH 2007 Chip Addressing Table 1 shows the bit assignments during the addressing cycle. Table 1. Address Selection Field BIT FUNCTION A7 Future expansion (value not compared) A6 Future expansion (value not compared) A5 Device address. Compared with pin A5 A4 Device address. Compared with pin A4 A3 Device address. Compared with pin A3 A2 Device address. Compared with pin A2 A1 Device address LSB.
TPS2384 www.ti.com SLUS634D – NOVEMBER 2004 – REVISED MARCH 2007 Table 2. Register/Port Addressing Map BIT FUNCTION STATE D7 Unused 0 D6 Register select MSB D5 Register select Bit 2 D4 Register select Bit 1 0000 = Common Read — Port fault status, chip ID and rev. 0001 = Common Control Write — Software reset, ports disable and AC Disc. 0010 = Port Control Write 1 — Function calls; misc.
TPS2384 www.ti.com SLUS634D – NOVEMBER 2004 – REVISED MARCH 2007 Table 4.
TPS2384 www.ti.com SLUS634D – NOVEMBER 2004 – REVISED MARCH 2007 Table 6. Port Control Write 1, Register Select = 0010 (One Per Port) BIT FUNCTION STATE PRESET STATE D7 Unused 0 0 D6 Unused 0 0 D5 Discovery fault disable 0 = normal operation 1 = disable internal discovery fault limits (19 kΩ to 29.
TPS2384 www.ti.com SLUS634D – NOVEMBER 2004 – REVISED MARCH 2007 Table 8.
TPS2384 www.ti.com SLUS634D – NOVEMBER 2004 – REVISED MARCH 2007 A/D Results Registers (Discovery Current, Voltage, Current and Temperature) Table 10. Discovery Current — Lower Bits, Register Select = 0110 (One Per Port) BIT FUNCTION D7 A/D bit 7 D6 A/D bit 6 D5 A/D bit 5 D4 A/D bit 4 D3 A/D bit 3 D2 A/D bit 2 D1 A/D bit 1 D0 A/D bit 0 STATE A/D lower bits PRESET STATE 0 Table 11.
TPS2384 www.ti.com SLUS634D – NOVEMBER 2004 – REVISED MARCH 2007 Table 13. Voltage — Upper Bits, Register Select = 1001 (One Per Port) BIT FUNCTION STATE PRESET STATE D7 Voltage measurement complete 0 = measurement active (bit set low when A/D begins a voltage measurement) 1 = measurement complete (bit set high after A/D has completed a voltage measurement) 0 D6 A/D bit 14 A/D upper bits 0 D5 A/D bit 13 D4 A/D bit 12 D3 A/D bit 11 D2 A/D bit 10 D1 A/D bit 9 D0 A/D bit 8 Table 14.
TPS2384 www.ti.com SLUS634D – NOVEMBER 2004 – REVISED MARCH 2007 Table 16. Temperature — Lower Bits, Register Select = 1100 (One Per Port) BIT FUNCTION D7 A/D bit 7 D6 A/D bit 6 D5 A/D bit 5 D4 A/D bit 4 D3 A/D bit 3 D2 A/D bit 2 D1 A/D bit 1 D0 A/D bit 0 STATE A/D lower bits PRESET STATE 0 Table 17.
TPS2384 www.ti.com SLUS634D – NOVEMBER 2004 – REVISED MARCH 2007 TPS2384 AC DRIVE APPLICATION SCHEMATIC AC_HI and LOW w/o External FET Configurations Figure 17.
TPS2384 www.ti.com SLUS634D – NOVEMBER 2004 – REVISED MARCH 2007 TPS2384 AC DRIVE APPLICATION SCHEMATIC (continued) TPS2384 System Block Diagram NOTE: A fuse may be required to provide additional protection if isolation is lost or the low-side current sense fails. Figure 18.
TPS2384 www.ti.com SLUS634D – NOVEMBER 2004 – REVISED MARCH 2007 TPS2384 AC DRIVE APPLICATION SCHEMATIC (continued) TPS2384 Basic 4 PORT (PMM) Isolated Configuration with AC Disconnect TPS2384 basic 4-port isolated configuration with AC Disconnect (PAP pinout shown). Function 7.5K Auto 68uF + 0.1uF 220pF 124K 0.1uF 0.1uF 0.1uF - 7.5K 7.5K 7.5K SYN AC_HI AC_LO Ct V2.5 RG Rbias AG1 V48 V6.3 V10 MS RJ45-5 Xformer 1 2 48 3 46 47 CINT4 45 RET4 44 4 CINT1 0.
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PACKAGE MATERIALS INFORMATION www.ti.com 26-Jan-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant TPS2384PAPR HTQFP PAP 64 1000 330.0 24.4 13.0 13.0 1.5 16.0 24.0 Q2 TPS2384PJDR HTQFP PJD 64 1000 330.0 24.4 13.0 13.0 1.5 16.0 24.
PACKAGE MATERIALS INFORMATION www.ti.com 26-Jan-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS2384PAPR HTQFP PAP 64 1000 367.0 367.0 45.0 TPS2384PJDR HTQFP PJD 64 1000 367.0 367.0 45.
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