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Data Read Cycles

TPS23841

SLUS745A – NOVEMBER 2006 – REVISED MAY 2007

For a data read sequence, after the register acknowledge bit, the master device generates a stop condition. This

is followed by a second start condition, and re-transmitting the device address as described in chip address

above. For this cycle, however, the R/W bit is set to a 1 to signal the read operation. The TPS23841 again

responds with an acknowledge pulse. The address acknowledge is then followed by sequentially presenting

each of the eight data bits on the SDA_O line (MSB first), to be read by the host device on the rising edges of

SCL. After eight bits are transmitted, the host acknowledges by pulling the SDA_I line high for one clock pulse.

The completed data transfer is terminated with the host generating a stop condition.

Table 2. Register/Port Addressing Map

BIT FUNCTION STATE PRESET

STATE

D7 Unused 0 0

D6 Register select MSB 0000 = Common Read - Port fault status, chip ID and rev.

0001 = Common Control Write - Software reset, ports disable and AC Disc.

D5 Register select Bit 2

0010 = Port Control Write 1 - Function calls; misc. fault disables

D4 Register select Bit 1

0011 = Port Control Write 2 - Port enable; A/D control

0100 = Port Status Read 1 - Fault status; device Class info.

0101 = Port Status Read 2 - Function and other status

0110 = Discovery Current - Lower Bits - A/D resistance results

0111 = Discovery Current - Upper Bits - A/D resistance results

0000

1000 = Voltage-Lower Bits - A/D voltage reslts

1001 = Voltage - Upper Bits - A/D voltage results

D3 Register select LSB

1010 = Current - Lower Bits - A/D current results

1011 = Current - Upper Bits - A/D current results

1100 = Temperature - Lower Bits - A/D temperature results

1101 = Temperature - Upper Bits - A/D temperature results

1110 = unused

1111 = Common Write - Test mode selections - timer disables, discovery control, etc.

D2 Unused 0 0

D1 Port address MSB 00 = port 1 00

01 = port 2

D0 Port address LSB

10 = port 3

11 = port 4

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