Datasheet

TPS2379
SLVSB98 –MARCH 2012 www.ti.com
DETAILED PIN DESCRIPTIONS
The following descriptions refer to the schematic of Figure 1 or Figure 4 and the functional block diagram.
CDB (Converter Disble Bar): This active low output is pulled to RTN when the device is in inrush current limiting,
going open when inrush period has completed once the GATE output has become higher than 6 V. This ensures
that the external pass transistor is enhanced before the load is enabled. It remains in a high impedance state at
all other times. This pin is an open-drain output, and it may require a pullup resistor or other interface to the
downstream load. CDB may be left open if it is not used.
CLS: An external resistor (R
CLS
in Figure 1) connected between the CLS pin and VSS provides a classification
signature to the PSE. The controller places a voltage of approximately 2.5 V across the external resistor
whenever the voltage differential between VDD and VSS lies between about 10.9 V and 22 V. The current drawn
by this resistor, combined with the internal current drain of the controller and any leakage through the internal
pass MOSFET, creates the classification current. Table 1 lists the external resistor values required for each of
the PD power ranges defined by IEEE802.3at. The maximum average power drawn by the PD, plus the power
supplied to the downstream load, should not exceed the maximum power indicated in Table 1.
High-power PSEs may perform two classification cycles if Class 4 is presented on the first cycle.
Table 1. Class Resistor Selection
CLASS MINIMUM POWER MAXIMUM POWER RESISTOR
AT PD (W) AT PD (W) R
CLS
(Ω)
0 0.44 12.95 1270
1 0.44 3.84 243
2 3.84 6.49 137
3 6.49 12.95 90.9
4 12.95 25.5 63.4
DEN (Detection and Enable): This pin implements two separate functions. A resistor (R
DEN
in Figure 1)
connected between V
DD
and DEN generates a detection signature whenever the voltage differential between V
DD
and V
SS
lies between approximately 1.4 and 10.9V. Beyond this range, the controller disconnects this resistor to
save power. For applications that wish to comply with the requirements of IEEE802.3at, the external resistance
should equal 24.9 kΩ.
If the resistance connected between V
DD
and DEN is divided into two roughly equal portions, then the application
circuit can disable the PD by grounding the tap point between the two resistances. This action simultaneously
spoils the detection signature and thereby signals the PSE that the PD no longer requires power.
GATE (Auxiliary Gate Driver): This pin allows the connection of an external pass MOSFET in parallel with the
internal pass transistor. The GATE pin enables the external transistor after inrush has completed. Current is
divided between the external MOSFET and the internal transistor as a function of their respective resistances.
The addition of a balancing resistor (R
BLST
in Figure 1) in series with RTN and the external MOSFET can ensure
desired distribution of the two currents. Whenever the RTN current exceeds the current limit threshold, the GATE
pin will pull low after a 365 µs delay. The GATE pin is pulled low in thermal shutdown. After the controller cools
down, and the inrush cycle is complete, the GATE pin rises again.
RTN: This pin provides the negative power return path for the load. Once V
DD
exceeds the UVLO threshold, the
internal pass MOSFET pulls RTN to VSS. Inrush limiting prevents the RTN current from exceeding about 140 mA
until the bulk capacitance (C
BULK
in Figure 1) is fully charged. Inrush ends when the RTN current drops below
about 125 mA. The RTN current is subsequently limited to about 1 A. CDB pulls low to signal the downstream
load that the bulk capacitance is fully charged. If RTN ever exceeds about 12 V for longer than 800 µs, then the
TPS2379 returns to inrush limiting.
T2P (Type-2 PSE Indicator): The controller pulls this pin to RTN whenever type-2 hardware classification has
been observed. The T2P output will return to a high-impedance state if the part enters thermal shutdown, the
pass MOSFET enters inrush limiting, or if a type-2 PSE was not detected. The circuitry that watches for type-2
hardware classification latches its result when the V
DD
-to-V
SS
voltage differential rises above the upper
classification threshold. This circuit resets when the V
DD
-to-V
SS
voltage differential drops below the mark
threshold. The T2P pin can be left unconnected if it is not used.
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