Datasheet

RTN
V
C
V
DD
V
SS
CDB
T2P
GATE
R
BLST
R
T2P
C
BULK
TPS2379
DC/DC Converter
SS
Q1
Q2
I
2379
I
L
BLST Q1
2 379 L
BLST Q 1 2379
R R
I I
R R R
+
= ´
+ +
TPS2379
SLVSB98 –MARCH 2012 www.ti.com
GATE Pin Interface
A non-standard PoE system can be designed to meet extended power requirements and retain the PoE benefits
such as protection of non – PoE devices and fault tolerance. Such a solution will not comply with IEEE802.3at
and should be designed and operated as stand-alone system. The TPS2379 GATE pin is used to control an
external pass MOSFET as shown in Figure 26. When inrush is complete, GATE sources 38µA to enable Q1, the
external pass MOSFET. When Q1 is fully enhanced, CDB de-asserts and enables the load. Delaying the de-
assertion of CDB until Q1 becomes fully enhanced prevents nuisance over-current faults that could occur with
heavy startup loads. A resistor from GATE to VSS is not required to ensure that Q1 turns off; but, if a resistor
from GATE to VSS is used, choose a value large enough so that the GATE sourcing current can fully enhance
Q1.
Figure 26. GATE Interface
EXTERNAL BOOST CIRCUIT (Q1, Q2, and R
BLST
) CONSIDERATIONS
As discussed above, the IEEE802.3at template bounds the peak PSE output current between 50A for 10 μs and
1.75 A for 75 ms for a two-pair system. In a non-standard, four-pair system these current levels can be assumed
to double. During an overload event, the TPS2379 will limit current to ~1A and the rest of the current will flow
through Q1 and R
BLST
. Ignoring the ballast resistor and parasitic impedances the current through Q1 could be as
high as 99A.
Actual system level behavior will be influenced by the circuit parasitic impedances, diode bridge impedance,
contact resistances, external MOSFET resistance, and input voltage droop during the overload event. The
impedances act to reduce the peak current as well as drop the voltage across Q1 during the overload event. The
designer must evaluate the overload performance of their system and ensure that the selected external MOSFET
safe operating area (SOA) is not violated during the output overload. The duration of the overload can be
terminated if the input voltage droop to the TPS2379 goes below the UVLO falling threshold (32V typical). When
UVLO occurs, the internal MOSFET is disabled, GATE goes low, and the external MOSFET is disabled. This
shortened overload duration is beneficial when evaluating the external MOSFET SOA performance.
Additional limiting and control of the external output overload current can be achieved by using the ballast
resistor, R
BLST
. R
BLST
is used to help balance the internal and external MOSFET load currents, and to implement
external current limiting through the use of Q2. The load current, I
L
divides between the external Q1 and the
internal pass MOSFET of the TPS2379 as shown in Equation 1.
(1)
R
Q1
is the ON resistance of Q1 and R
2379
is the ON resistance of the TPS2379. Q2 can be used to force Q1 to
limit its current when the voltage across R
BLST
exceeds V
BEON
of Q2. Further discussion of these details, as well
as additional considerations involving PD classification, are discussed in the application report Implementing a 60
W end-to-end PoE system (literature number SLVA498).
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