Datasheet

Time: 5ms/div
10V/div
100mA/div
I
PI
Inrush
Load enabled using
CDB plus delay
V
VDD-RTN
V
CDB-RTN
V
T2P-RTN
50V/div
50V/div
PI powered
Type 1 PSE
Type 2 PSE
V
(GATE -VSS)
10V/div
TPS2379
www.ti.com SLVSB98 –MARCH 2012
Figure 22. Power Up and Start
PD Hotswap Operation
IEEE 802.3at has taken a new approach to PSE output limiting. A type 2 PSE must meet an output current
versus time template with specified minimum and maximum sourcing boundaries. The peak output current may
be as high as 50 A for 10 μs or 1.75 A for 75 ms. This makes robust protection of the PD device even more
important than it was in IEEE 802.3-2008.
The internal hotswap MOSFET is protected against output faults and input voltage steps with a current limit and
deglitched (time-delay filtered) foldback. An overload on the pass MOSFET engages the current limit, with V
RTN
-
V
VSS
rising as a result. GATE is pulled down about 300 μs after RTN current reaches the current limit level. If
V
RTN
rises above ~12 V for longer than ~800 μs, the current limit reverts to the inrush value. The 800 μs deglitch
feature prevents momentary transients from causing a PD reset, provided that recovery lies within the bounds of
the hotswap and PSE protection. Figure 23 shows an example of the RTN current profile during VDD to RTN
short circuit when only the internal hotswap MOSFET is used. The hotswap MOSFET goes into current limit,
causing the RTN voltage to increase. Once V
RTN
exceeds 12V, I
RTN
which was clamped to the current limit drops
to the level of inrush current limit after 800µs.
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