Datasheet

Detect Class
Mark Class
Mark Class
Between
Ranges
Between
Ranges
Operating
T2P
open-drain
Operating
T2P low
Between
Ranges
UVLO
Rising
UVLO
Falling
UVLO
Rising
UVLO
Falling
TYPE 2 PSE
Hardware Class
Class
TYPE 1 PSE
Hardware Class
Between
Ranges
PoE Startup Sequence
Mark
Reset
Idle
TPS2379
SLVSB98 –MARCH 2012 www.ti.com
Figure 21. Two-Event Class Internal States
Inrush and Startup
IEEE 802.3at has a startup current and time limitation, providing type 2 PSE compatibility for type 1 PDs. A type
2 PSE limits output current to between 400 mA and 450 mA for up to 75 ms after power-up (applying “48 V” to
the PI) in order to mirror type 1 PSE functionality. The type 2 PSE will support higher output current after 75 ms.
The TPS2379 implements a 140 mA inrush current, which is compatible with all PSE types. A high-power PD
must limit its converter startup peak current. The operational current cannot exceed 400 mA for a period of 80 ms
or longer. This requirement implicitly requires some form of powering down sections of the application circuits.
Maintain Power Signature
The MPS is an electrical signature presented by the PD to assure the PSE that it is still present after operating
voltage is applied. A valid MPS consists of a minimum dc current of 10 mA (or a 10 mA pulsed current for at
least 75 ms every 325 ms) and an ac impedance lower than 26.3 kΩ in parallel with 0.05 μF. The ac impedance
is usually accomplished by the minimum operating C
BULK
requirement of 5 μF. When DEN is used to force the
hotswap switch off, the dc MPS will not be met. A PSE that monitors the dc MPS will remove power from the PD
when this occurs. A PSE that monitors only the ac MPS may remove power from the PD.
Startup and Operation
The internal PoE UVLO (Under Voltage Lock Out) circuit holds the hotswap switch off before the PSE provides
full voltage to the PD. This prevents the downstream converter circuits from loading the PoE input during
detection and classification. The converter circuits will discharge C
BULK
while the PD is unpowered. Thus V
(VDD-
RTN)
will be a small voltage just after full voltage is applied to the PD, as seen in Figure 20. The PSE drives the PI
voltage to the operating range once it has decided to power up the PD. When V
VDD
rises above the UVLO turn-
on threshold (V
UVLO-R
, ~38 V) with RTN high, the TPS2379 enables the hotswap MOSFET with a ~140 mA
(inrush) current limit as seen in Figure 22. The CDB pin is active while C
BULK
charges and V
RTN
falls from V
VDD
to
nearly
VVSS
. Once the inrush current falls about 10% below the inrush current limit, the PD current limit switches
to the operational level (~1000 mA) and CDB is deasserted to allow downstream converter circuitry to start. The
TPS2379 asserts GATE after inrush is complete to enable an external pass MOSFET if used. In Figure 22, T2P
is active because a type 2 PSE is plugged in.
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