Datasheet

TPS2378
SLVSB99B –MARCH 2012–REVISED NOVEMBER 2013 www.ti.com
Table 1. Class Resistor Selection
CLASS MINIMUM POWER MAXIMUM POWER RESISTOR R
CLS
AT PD (W) AT PD (W) (Ω)
0 0.44 13 1270
1 0.44 3.84 243
2 3.84 6.49 137
3 6.49 13 90.9
4 13 25.5 63.4
DEN (Detection and Enable): This pin implements two separate functions. A resistor (R
DEN
in Figure 1)
connected between V
DD
and DEN generates a detection signature whenever the voltage differential between V
DD
and V
SS
lies between approximately 1.4 and 10.9V. Beyond this range, the controller disconnects this resistor to
save power. For applications that wish to comply with the requirements of IEEE802.3at, the external resistance
should equal 24.9 kΩ.
If the resistance connected between V
DD
and DEN is divided into two roughly equal portions, then the application
circuit can disable the PD by grounding the tap point between the two resistances. This action simultaneously
spoils the detection signature and thereby signals the PSE that the PD no longer requires power.
RTN: This pin provides the negative power return path for the load. Once V
DD
exceeds the UVLO threshold, the
internal pass MOSFET pulls RTN to V
SS
. Inrush limiting prevents the RTN current from exceeding about 140 mA
until the bulk capacitance (C
BULK
in Figure 1) is fully charged. Inrush ends when the RTN current drops below
about 125 mA. The RTN current is subsequently limited to about 1 A. CDB pulls low to signal the downstream
load that the bulk capacitance is fully charged. If RTN ever exceeds about 12 V for longer than 800 µs, then the
TPS2378 returns to inrush limiting.
T2P (Type-2 PSE Indicator): The controller pulls this pin to RTN whenever type-2 hardware classification has
been observed or the APD pin is pulled high. The T2P output will return to a high-impedance state if the part
enters thermal shutdown, the pass MOSFET enters inrush limiting, or if a type-2 PSE was not detected and the
voltage on APD drops below its threshold. The circuitry that watches for type-2 hardware classification latches its
result when the V
DD
-to-V
SS
voltage differential rises above the upper classification threshold. This circuit resets
when the V
DD
-to-V
SS
voltage differential drops below the mark reset threshold. The T2P pin can be left
unconnected if it is not used.
V
DD
: This pin connects to the positive side of the input supply. It provides operating power to the PD controller
and allows monitoring of the input line voltage.
V
SS
: This is the input supply negative rail that serves as a local ground. The PowerPad™ must be connected to
this pin to ensure proper operation.
PowerPAD
The PowerPAD is internally connected to V
SS
. It should be tied to a large V
SS
copper area on the PCB to provide
a low resistance thermal path to the circuit board. It is recommended that a clearance of 0.025” be maintained
between V
SS
and high-voltage signals such as V
DD
.
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