Datasheet

12V and
10V
22V and
21.25V
38.1V and
32V
V
DD
1
0
S
R
Q
Inrush limit
threshold
Current limit
threshold
RTN
CLS
APD
V
SS
DEN
800ms
2.5V
REG.
Detection
Comp.
4V
1.5Vand
1.2V
Hotswap
MOSFET
Class
Comp.
Mark
Comp.
APD
Comp.
12V
UVLO
Comp.
OTSD
I sense,1 if < 90% of inrush current limit
RTN
1 = inrush
Signals referenced to V
SS
unless otherwise noted
1
8
4 5
3
2
Class
Comp.
5V and 4V
0 = current limit
Inrush latch
RTN
800ms
1
0
I
RTN
sense
RTN
Type 2
State Eng.
Mark Comp Output
UVLO Comp Output
7
T2P
V
SS
S
R
Q
RTN
RTN
6
CDB
High if over
temperauture
V
SS
TPS2378
www.ti.com SLVSB99B –MARCH 2012–REVISED NOVEMBER 2013
Figure 2. Functional Block Diagram
DETAILED PIN DESCRIPTION
The following descriptions refer to the schematic of Figure 1 and Figure 2.
APD (Auxiliary Power Detect): This pin is used in applications that may draw power either from the Ethernet
cable or from an auxiliary power source. A voltage of more than about 1.5 V on the APD pin relative to RTN turns
off the internal pass MOSFET, disables the CLS output, and enables the T2P output. A resistor divider
(R
APD1
–R
APD2
in Figure 1) provides system-level ESD protection for the APD pin, discharges leakage from the
blocking diode (D
A
in Figure 1) and provides input voltage supervision to ensure that switch-over to the auxiliary
voltage source does not occur at excessively low voltages. If not used, connect APD to RTN.
CDB (Converter Disable Bar): This active low output is pulled to RTN when the device is in inrush current
limiting. It remains in a high impedance state at all other times. This pin is an open-drain output, and it may
require a pullup resistor or other interface to the downstream load. CDB may be left open if it is not used.
CLS: An external resistor (R
CLS
in Figure 1) connected between the CLS pin and V
SS
provides a classification
signature to the PSE. The controller places a voltage of approximately 2.5 V across the external resistor
whenever the voltage differential between V
DD
and VSS lies between about 10.9 V and 22 V. The current drawn
by this resistor, combined with the internal current drain of the controller and any leakage through the internal
pass MOSFET, creates the classification current. Table 1 lists the external resistor values required for each of
the PD power ranges defined by IEEE802.3at. The maximum average power drawn by the PD, plus the power
supplied to the downstream load, should not exceed the maximum power indicated in Table 1. Holding APD high
disables the classification signature.
High-power PSEs may perform two classification cycles if Class 4 is presented on the first cycle.
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