Datasheet

Time: 200 s/divm
500 mA/div
I
PI
Inrush
V > 12 V
RTN-VSS
20 V/div
V
RTN-VSS
V
CDB-VSS
20 V/div
Time: 5 ms/div
100 mA/div
I
PI
Inrush
Load enabled using
CDB plus delay
V
VDD-RTN
V
CDB-RTN
V
T2P-RTN
50 V/div
PI powered
Type 1 PSE
Type 2 PSE
50 V/div
10 V/div
TPS2378
www.ti.com SLVSB99B –MARCH 2012–REVISED NOVEMBER 2013
Figure 21. Power Up and Start
PD Hotswap Operation
IEEE 802.3at has taken a new approach to PSE output limiting. A type 2 PSE must meet an output current vs.
time template with specified minimum and maximum sourcing boundaries. The peak output current may be as
high as 50 A for 10 μs or 1.75 A for 75 ms. This makes robust protection of the PD device even more important
than it was in IEEE 802.3-2008.
The internal hotswap MOSFET is protected against output faults and input voltage steps with a current limit and
deglitched (time-delay filtered) foldback. An overload on the pass MOSFET engages the current limit, with V
(RTN-
VSS)
rising as a result. If V
(RTN-VSS)
rises above ~12 V for longer than ~800 μs, the current limit reverts to the
inrush value. The 800 μs deglitch feature prevents momentary transients from causing a PD reset, provided that
recovery lies within the bounds of the hotswap and PSE protection. Figure 22 shows an example of the RTN
current profile during V
DD
to RTN short circuit. The hotswap MOSFET goes into current limit, causing the RTN
voltage to increase. Once V
RTN
exceeds 12V, I
RTN
which was clamped to the current limit drops to the level of
inrush current limit after 800µs. The inrush current limit is re-established when V
(VDD-VSS)
drops below UVLO.
Figure 22. Response to PD Output Short Circuit
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